Method and circuit for preventing overshoot of phase-locked loop clock and clock generation device

Abstract

The invention relates to a method and circuit for preventing overshoot of a phase-locked loop clock and a clock generation device. The method comprises the steps: acquiring an input signal and a feedback signal of the phase-locked loop, determining the current state of the phase-locked loop according to the input signal and the feedback signal, wherein the state of the phase-locked loop comprisesa locked state and an unlocked state; when the current state is an unlocked state, performing frequency reduction processing on the output signal of the phase-locked loop, and taking the signal afterfrequency reduction processing as a clock signal; when the current state is a locked state, directly taking the output signal of the phase-locked loop as a clock signal. By implementing the technicalscheme of the invention, the available clock can be provided more reliably and quickly at lower cost, the software running efficiency can be improved, and the power consumption can be saved.

Description

technical field [0001] The invention relates to the field of phase-locked loops, in particular to a method, circuit and clock generating device for preventing phase-locked loop clock overshoot. Background technique [0002] The phase-locked loop is a feedback control circuit, called a phase-locked loop (Phase-Locked Loop, PLL for short). He uses the externally input reference signal to control the frequency and phase of the internal oscillation signal of the loop. In the process of processing electronic signals, because the phase-locked loop can automatically track the frequency of the output signal to the frequency of the input signal, the phase-locked loop is usually widely used in closed-loop tracking circuits. In the field of clocks, clock phase-locked loops are widely used in clock generation. [0003] combine figure 1 The clock phase-locked loop shown usually consists of several parts: phase detector PD, loop filter LPF, voltage-controlled oscillator VCO and loop fr...

AI Technical Summary

Problems solved by technology

For example, the input reference frequency of a phase-locked loop is 12.5MHz, when the frequency divider coefficient is changed from 31 to 60, such as figure 2 As shown, the output frequency should change from 387.5MHz (12.5*31) to 750MHz (12.5*60). When the frequency changes, the second-order damped oscillation characteristics can be clearly seen, and due to the overshoot of the oscillation, there is an output of 780MHz during the period. The frequency is greater than the target value of 750MHz, and if the output frequency of 780MHz exceeds the maximum operating frequency of the system (for example, only 770MHz), it may cause system errors or even crash

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