System-in-package method and structure of heterogeneous integrated chip
A system-level packaging and integrated chip technology, which is applied in the manufacture of electrical components, electrical solid devices, semiconductor/solid devices, etc., can solve the problems that heterogeneous chips cannot be integrated and packaged, so as to reduce process costs, reduce costs, and reduce process difficulty Effect
- Summary
- Abstract
- Description
- Claims
- Application Information
AI Technical Summary
Problems solved by technology
Method used
Image
Examples
Example Embodiment
[0047]
[0048] This embodiment provides a system-in-package method for heterogeneous integrated chips, such as Figure 1~10 As shown, the system-in-package method of the heterogeneous integrated chip includes: manufacturing a plurality of silicon substrate chips 10; backing of the plurality of silicon substrate chips 10 to a carrier 20 and intensively pasting on the carrier 20, Form the first integrated transfer board 101; figure 2 As shown, a first plastic encapsulation layer 30 is formed on the first integrated transfer board 101, and the silicon substrate chip 10 and the first plastic encapsulation layer 30 form a first plastic encapsulation body 102; image 3 As shown, performing a mechanical or chemical polishing process on the top of the first plastic package body 102 exposes a plurality of electrical lead-out portions 11 of the silicon substrate chip 10; Figure 4 As shown, a metal interconnection layer and a dielectric layer 40 are fabricated on top of a plurality of the ...
Example Embodiment
[0059]
[0060] This embodiment also provides a system-in-package structure for heterogeneous integrated chips, such as Figure 7 As shown, it includes: a plurality of silicon substrate chips 10; a first plastic encapsulation layer 30 covering the top of the silicon substrate chip 10 and the carrier sheet 20; The electrical lead-out portion 11 is exposed on the top of the first plastic encapsulation layer 30; a metal interconnection layer and a dielectric layer 40 are located on the top of the first plastic encapsulation layer 30, and the metal interconnection layer and a plurality of the silicon substrates The electrical lead-out portion 11 of the chip 10 is electrically connected; a plurality of heterogeneous chips 50 located on top of the metal interconnection layer and the dielectric layer 40 and electrically connected to the metal interconnection layer and the dielectric layer 40, the heterogeneous chip The absolute height of 50 is the same. In another embodiment of the pr...
PUM
Property | Measurement | Unit |
---|---|---|
Thickness | aaaaa | aaaaa |
Thickness | aaaaa | aaaaa |
Abstract
Description
Claims
Application Information
- R&D Engineer
- R&D Manager
- IP Professional
- Industry Leading Data Capabilities
- Powerful AI technology
- Patent DNA Extraction
Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic.
© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap