Semi-floating gate memory based on pn junction and Schottky diode and its preparation method

Abstract

The invention belongs to the technical field of integrated circuit memory, in particular to a semi-floating gate memory based on a pn junction and a Schottky diode and a preparation method thereof. The semi-floating gate memory disclosed by the present invention is to embed a pn junction and a Schottky diode inside the floating gate transistor at the same time, as channels for charge erasing and writing respectively; The voltage is very small; using the pn junction as the channel for charge erasing can greatly increase the erasing speed; Schottky diodes also have rectification characteristics, and the turn-on voltage is also very small; using Schottky diodes as the channel for charge writing, The charge writing speed can be greatly improved.

Description

technical field [0001] The invention belongs to the technical field of integrated circuit memory, and in particular relates to a semi-floating gate memory based on a pn junction and a Schottky diode and a preparation method thereof. Background technique [0002] At present, DRAM devices used in integrated circuit chips are mainly 1T1C structures, that is, a transistor is connected in series with a capacitor, and the capacitor is charged and discharged through the switch of the transistor, thereby realizing the conversion between DRAM devices 0 and 1. As the device size becomes smaller and smaller, DRAM devices used in integrated circuit chips are facing more and more problems. For example, DRAM devices require 64 ms to refresh once, so the capacitance value of the capacitor must be kept above a certain value to ensure sufficient Long charge retention time, but as the feature size of integrated circuits shrinks, the manufacture of large capacitors has become more and more dif...

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Problems solved by technology

However, the tunneling transistor is a minority current device, which means that the driving current of the tunneling transistor is small, which will affect the erasing speed of the semi-floating gate transistor.

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