A hinoc channel bonding method, chip and device
A channel bonding and chip technology, applied in the field of communication, can solve problems such as insufficient utilization of effective bandwidth, interference, limited isolation, etc., and achieve the effects of pattern synchronization, pattern load balancing, and system time synchronization
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Embodiment 1
[0056] An embodiment of the present disclosure provides a HINOC channel binding method, figure 1It is a schematic flowchart of a HINOC channel bonding method according to an exemplary embodiment. Such as figure 1 Shown, a kind of HINOC channel bonding method comprises:
[0057] S101 performs analog bandwidth configuration and frequency spectrum configuration on each central office module in the HINOC channel binding central office equipment;
[0058] Specifically, the occupied analog bandwidth of each central office module in the HINOC channel bonding central office is 128MHz, and the frequency spectrums of different central office modules cannot overlap, otherwise co-channel interference will be caused.
[0059] S102 Configure each central office module in the central office device with an independent media access control layer processing unit and an independent physical layer processing unit;
[0060] Specifically, each central office module in each central office device ...
Embodiment 2
[0072] An embodiment of the present disclosure provides a single-channel HINOC local end chip, image 3 It is a schematic structural diagram of a single-channel HINOC local end chip according to an exemplary embodiment.
[0073] Such as image 3 As shown, a single-channel HINOC local end chip includes:
[0074] The embedded central processing unit is used to control the overall workflow of the chip; including chip parameter configuration, communication link maintenance, communication parameter calculation, network management protocol processing, etc.
[0075] Peripheral interface for data interaction with external chips or devices;
[0076] Among them, the peripheral interface includes various commonly used peripheral interfaces, including but not limited to I 2 C (Inter-Integrated Circuit) bus interface, UART (Universal Asynchronous Receiver Transmitter, Universal Asynchronous Receiver Transmitter) bus interface, SPI (serial peripheral interface, serial peripheral interfac...
Embodiment 3
[0090] An embodiment of the present disclosure provides a HINOC central office chip.
[0091] In some exemplary scenarios, a HINOC central office chip includes:
[0092] More than two central office modules, wherein each central office module includes the embedded central processing unit, peripheral interface, data bus, channel bonding processing module, digital-to-analog converter, analog-to-digital converter, Clock management, reset management and power management modules, Ethernet interface, media access control layer processing unit, physical layer processing unit;
[0093] Use any central office module as the master central office module, and the other central office modules as slave central office modules. When there are multiple slave end modules, they can be numbered to facilitate their processing.
[0094] Among them, each central office module occupies a 128MHz frequency band and cannot overlap with each other, otherwise it will cause co-frequency interference.
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