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FPGA single event upset error correction method and circuit

A technology of single event flipping and error correction method, which is applied in the field of integrated circuit design and anti-radiation hardening design, can solve the problems of inability to configure the address of readback frame data and false report of readback data, so as to avoid data false report and increase The effect of flexibility

Active Publication Date: 2020-08-28
SHANGHAI ANLOGIC INFOTECH CO LTD
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Problems solved by technology

[0007] The purpose of this application is to provide an FPGA single event flip error correction method and circuit, electronic equipment, and computer-readable storage medium, so as to solve the problem that when the existing error correction circuit performs ECC operation, the user must check all the frames in the FPGA, and cannot be configured to return Read the address of the frame data, which may cause false positives in the readback data

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  • FPGA single event upset error correction method and circuit
  • FPGA single event upset error correction method and circuit
  • FPGA single event upset error correction method and circuit

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Embodiment Construction

[0031] Below, the present application will be further described in conjunction with the accompanying drawings and specific implementation methods. It should be noted that, on the premise of not conflicting, the various embodiments described below or the technical features can be combined arbitrarily to form a new embodiment. .

[0032] see figure 1 , the embodiment of the present application provides an FPGA single event flip error correction method, which is suitable for SRAM-type FPGA single event flip error correction design, and the method includes steps S101-S103.

[0033] Step S101: Detect whether the configuration data frame address is a frame address that does not require ECC verification.

[0034] In some possible implementation manners, frame addresses that do not require ECC verification may be detected by configuring whether the data frame addresses comply with a masking rule. Specifically, the step S101 may include: detecting whether the configuration data frame...

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Abstract

The invention discloses an FPGA single event upset error correction method and circuit, electronic equipment and a computer readable storage medium. The method comprises the steps of detecting whethera configuration data frame address is a frame address without ECC verification or not; if the configuration data frame address is the frame address which does not need ECC verification, not performing ECC verification on the configuration data frame corresponding to the configuration data frame address; If the configuration data frame address is not the frame address which does not need ECC verification, performing ECC verification on the configuration data frame corresponding to the configuration data frame address. In the SEU error correction process, the SEU error is corrected; a user canconfigure the frame address which does not need ECC verification, for example, the frame address which easily generates misinformation can be configured to be the frame address which does not need ECCverification, and for the frame address which does not need verification, data read-back and ECC verification are not carried out, so that the flexibility of ECC verification is improved, and data misinformation possibly caused by noise is avoided.

Description

technical field [0001] This application relates to the technical field of integrated circuit design and anti-radiation hardening design, in particular to FPGA single event flip error correction method and circuit, electronic equipment, and computer-readable storage medium. Background technique [0002] Single Event Upset (SEU, Single Event Upset) is caused by space particle radiation causing a bit flip in a storage unit (that is, the content changes from 0 to 1, or from 1 to 0). The SEU effect is transient and non-destructive, but it may change the RAM (Random Access Memory) configuration of microelectronic circuits, and adversely affect the functions performed by programmable electronic hardware. [0003] Modern civil aircraft flight control, avionics and other systems are highly complex, and a large number of complex electronic devices based on RAM are used. Such as microprocessors, Field Programmable Gate Arrays FPGA (Field Programmable Gate Arrays) and so on. At presen...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F11/10
CPCG06F11/1048
Inventor 赫艳红
Owner SHANGHAI ANLOGIC INFOTECH CO LTD