Clock phase alignment method and circuit for high-speed serial transceiver

Abstract

The invention discloses a clock phase alignment method and circuit for a high-speed serial transceiver. The method comprises the steps: 1, in N reference clock signal periods, sampling a parallel clock signal of a to-be-processed channel to obtain N sampling results, wherein the sampling results are first numerical values or second numerical values, and N is larger than 1; 2, determining a counting result according to the number of the first numerical values in the N sampling results; 3, adjusting the phase of the parallel clock signal for multiple times, and repeating the step 1 and the step2 after each adjustment to obtain a plurality of counting results with numerical values from 0 to N; 4, drawing a relation curve of the delay time and the corresponding counting result; 5, performingphase adjustment on the parallel clock signal according to delay time corresponding to a rising edge or a falling edge of the relation curve; and 6, repeating the step 1 to the step 5 for other to-be-processed channels. According to the scheme provided by the invention, the resource consumption is low, the precision is high, and the time delay can still be flexibly adjusted as required after eachchannel is aligned.

Description

technical field [0001] The invention relates to the field of high-speed serial transceivers, in particular to a clock phase alignment method and circuit for high-speed serial transceivers. Background technique [0002] FPGA is a master of digital circuits, through its large number of general-purpose input and output pins, it can generate a variety of digital pulses. However, due to the limitation of FPGA global clock speed, the clock speed of this direct pulse generation method has been limited to below 400MHz to 500MHz for a long time. As the application fields of high-speed pulses with a clock speed exceeding 1 GHz become wider and wider, in order to generate such high-speed pulses, people have focused their attention on high-speed serial transceivers integrated with FPGAs. [0003] refer to figure 1 Shown is a schematic structural diagram of a multi-channel high-speed serial transceiver. The high-speed serial transceiver sends the parallel data bit by bit serially at a...

AI Technical Summary

Problems solved by technology

This solution has high precision, but it needs to realize high-precision TDC in FPGA, which is more complicated to realize and takes up more resources.

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