Manufacturing method of three-dimensional memory and three-dimensional memory manufactured by same

Abstract

The invention relates to a manufacturing method of a three-dimensional memory and the three-dimensional memory manufactured by the same. The manufacturing method according to the present disclosure includes the steps: forming a channel through hole in a longitudinal stack formed on a substrate, wherein the channel through hole extends from an upper layer of the longitudinal stack to the substratebelow the longitudinal stack, and the longitudinal stack is used for forming a circuit structure including an upper selection transistor, a memory cell string, and a lower selection transistor; depositing a first channel layer of the lower selection transistor on the bottom of the channel through hole; depositing a gate stack on the side wall of the channel through hole and the first channel layer; removing the gate stack on the first channel layer and a part of the first channel layer along the gate stack on the side wall of the channel through hole; depositing a second channel layer of the storage unit string in the channel through hole; and filling the channel through hole with a filling material.

Description

technical field [0001] The present disclosure relates to the technical field of semiconductor manufacturing, and more particularly, to a manufacturing method of a three-dimensional memory and a three-dimensional memory manufactured by the manufacturing method. According to the manufacturing method of the present disclosure, good ohmic contact between the channel layer of the memory cell string in the channel via hole of the three-dimensional memory and other components can be ensured. Background technique [0002] As the demand for highly integrated electronic devices continues to increase, semiconductor memory devices capable of operating at higher speeds and lower power consumption and having higher device densities are required. However, the further integration of traditional planar memories encounters bottlenecks, such as physical size limitations, development limitations of processing equipment such as photolithography machines, and electron density limitations of memor...

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Problems solved by technology

However, this ion implantation process requires high process stability. If process parameters fluctuate, it will easily cause the contact resistance between the channel layer of the memory cell string and the bit line contact point to be too high or too low, thus causing the entire The on-resistance of the circuit structure changes, which affects the stability of the device

[0012] Furthermore, such as As shown in Figure 2, the channel layer of the memory cell string will be partially lost during the etching step in the process flow. If the contact between it and the plug layer is poor, the ion implantation process will be difficult to further Reduce contact resistance

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