Shared cache method, baseband processing unit and chip thereof

A shared cache and cache unit technology, applied in the direction of electrical digital data processing, architecture with a single central processing unit, general-purpose stored program computer, etc., can solve the problems of increased chip design area and power consumption, and low efficiency of sampling point cache utilization , to reduce cache power consumption, facilitate miniaturization design, and improve utilization

Active Publication Date: 2021-01-15
长沙金维信息技术有限公司
View PDF10 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0007] Therefore, in the prior art, the total capacity requirement of all sampling point buffers is 1MB, resulting in a sharp increase in chip design area and power consumption
In practical applications, tracking high sampling rate, all tracking subsystems are concurrent, and tracking full channel multiplexing; therefore, in the traditional cache independent design, the utilization efficiency of the sampling point cache is low

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Shared cache method, baseband processing unit and chip thereof
  • Shared cache method, baseband processing unit and chip thereof
  • Shared cache method, baseband processing unit and chip thereof

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0037] Such as figure 2 Shown is a schematic flow chart of the method of the present invention: the shared cache method provided by the present invention includes the following steps:

[0038] S1. Set up the shared buffer area shared by the capture subsystem and several tracking subsystems (such as image 3 shown);

[0039] S2. According to the number of access requests, design the shared buffer area obtained in step S1; specifically, there are A-way tracking subsystem and B-way capture subsystem; each way tracking subsystem has a1 write requests and a2 read requests , and a1+a2 requests of each tracking subsystem simultaneously access the same buffer area; each capture subsystem has b1 write requests, b2 read requests, and each capture subsystem has b1+b2 requests Time-sharing access to the same batch of cache intervals; a total of C KB is designed for the shared cache interval, and is divided into D cache units, each cache unit is E KB; A, B, a1, a2, b1, b2, C, D, and E a...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

PUM

No PUM Login to view more

Abstract

The invention discloses a shared cache method, which includes setting a shared cache area shared by a capture subsystem and several tracking subsystems; designing the shared cache area according to the number of access requests; performing tracking access control, capture access control and cache clock control . The invention also discloses a baseband processing unit including the shared buffer method, and a chip including the shared buffer method and the baseband processing unit. The present invention effectively improves the utilization rate of the sampling point cache and effectively reduces the cache capacity by sharing the cache unit and controlling the shared cache unit; at the same time, the present invention can effectively reduce the cache area of ​​the chip, which is beneficial to the chip The miniaturization design; at the same time, the invention improves the utilization rate and uniformity of the buffer design, and reduces the power consumption of the buffer, and has high reliability and good practicability.

Description

technical field [0001] The invention belongs to the field of chip design, and in particular relates to a shared cache method, a baseband processing unit and a chip thereof. Background technique [0002] With the development of economy and technology and the improvement of people's living standards, navigation has become an indispensable auxiliary function in people's production and life, bringing endless convenience to people's production and life. [0003] In the high-precision navigation chip, the baseband processing unit mainly includes two parts: the capture subsystem and the tracking subsystem. In order to support the application scenarios of multiple systems and multiple frequency points, especially for the high-end requirements of positioning and orientation, the high-precision navigation chip needs to support the feature of simultaneous tracking of multiple frequency points, and multiple tracking subsystems are introduced. In order to support the multi-channel featu...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

Application Information

Patent Timeline
no application Login to view more
Patent Type & Authority Patents(China)
IPC IPC(8): G06F15/78
CPCG06F15/781Y02D10/00
Inventor 朱佳沈家瑞丁杰文承淦刘勇黄维陈宇蒋云翔
Owner 长沙金维信息技术有限公司
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Try Eureka
PatSnap group products

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic.

© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap