Shared cache method, baseband processing unit and chip thereof

Abstract

The invention discloses a shared cache method, which includes setting a shared cache area shared by a capture subsystem and several tracking subsystems; designing the shared cache area according to the number of access requests; performing tracking access control, capture access control and cache clock control . The invention also discloses a baseband processing unit including the shared buffer method, and a chip including the shared buffer method and the baseband processing unit. The present invention effectively improves the utilization rate of the sampling point cache and effectively reduces the cache capacity by sharing the cache unit and controlling the shared cache unit; at the same time, the present invention can effectively reduce the cache area of ​​the chip, which is beneficial to the chip The miniaturization design; at the same time, the invention improves the utilization rate and uniformity of the buffer design, and reduces the power consumption of the buffer, and has high reliability and good practicability.

Description

technical field [0001] The invention belongs to the field of chip design, and in particular relates to a shared cache method, a baseband processing unit and a chip thereof. Background technique [0002] With the development of economy and technology and the improvement of people's living standards, navigation has become an indispensable auxiliary function in people's production and life, bringing endless convenience to people's production and life. [0003] In the high-precision navigation chip, the baseband processing unit mainly includes two parts: the capture subsystem and the tracking subsystem. In order to support the application scenarios of multiple systems and multiple frequency points, especially for the high-end requirements of positioning and orientation, the high-precision navigation chip needs to support the feature of simultaneous tracking of multiple frequency points, and multiple tracking subsystems are introduced. In order to support the multi-channel featu...

AI Technical Summary

Problems solved by technology

[0007] Therefore, in the prior art, the total capacity requirement of all sampling point buffers is 1MB, resulting in a sharp increase in chip design area and power consumption

In practical applications, tracking high sampling rate, all tracking subsystems are concurrent, and tracking full channel multiplexing; therefore, in the traditional cache independent design, the utilization efficiency of the sampling point cache is low

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