Data-outputting buffer circuit

Abstract

Data-outputting buffer circuit suitable for reducing noise which is generated in an output buffer circuit part when minus electric filed is applied to a data output pad in inputting data is disclosed, including a noise generation restraining part detecting a level of a signal applied to an input / output pad inputting and outputting data for outputting first and second noise generation restraining signals, a pullup transistor having a source connected to the input / output pad and a drain electrode connected to a power voltage terminal, a pulldown transistor serially connected to the pullup transistor with both sources of the pullup and pulldown transistors connected to the input / output pad, first and second driving parts for driving the pullup transistor and the pulldown transistor, and a clamp transistor turned on by the first noise generation restraining signal for restraining increase of substrate bias due to voltage difference between a gate and the source of the pullup transistor.

Description

technical field [0001] The present invention relates to a data output buffer circuit, and more particularly to a data output buffer circuit capable of reducing noise generated in an output buffer circuit portion when a negative electric field is applied to a data output terminal in input data. Background technique [0002] A buffer is a temporary storage location where data is received or transferred between two devices or two programs with different rates and different units for processing the data. It acts to temporarily send a gate delay signal in a logic circuit. [0003] In a semiconductor memory device, a data output buffer circuit is used to output data read from a memory cell to an external chip. When a semiconductor memory device with high integration and high-speed operation is applied, noise occurs accompanying the operation of outputting data. One of the main reasons for its occurrence of noise is caused by a large peak current generated when a large-sized tran...

AI Technical Summary

Problems solved by technology

[0012] When the clamp transistor 4 is turned on due to the negative potential applied to the input / output terminal 1 and discharges the charge accumulated on the gate of the pull-up transistor 2 to the input / output terminal 1, the charge is again transferred from the first driving section to the input / output terminal 1. The source of the NMOS M4 of 5 is provided to the gate of the pull-up transistor 2, so that the resistor R1 delays the charge accumulation time of the gate of the pull-up transistor 2 when outputting data, thus causing a delay in the pull-up operation

Therefore, it is impossible to effectively suppress the noise generated by the increase of the substrate bias potential due to the large difference between the drain and the source of the pull-up transistor 2

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