FPGA device with power-on reset signal waveform adjustable function

Abstract

The invention discloses an FPGA device with a power-on reset signal waveform adjustable function and relates to the technical field of FPGA. The FPGA device comprises an FPGA die. The FPGA die comprises a power-on reset circuit, a power utilization circuit and a reset signal control module. The input end of the reset signal control module is connected with the output end of the power-on reset circuit and acquires a first power-on reset pulse signal output by the power-on reset circuit; the reset signal control module selects one control signal from a plurality of control signals acquired by the control end to adjust the waveform of the first power-on reset pulse signal to obtain a second power-on reset pulse signal, and outputs the second power-on reset pulse signal to the power utilization circuit; therefore, the power-on process of the power utilization circuit in the FPGA die is influenced, and the sources of the control signals of the reset signal control module are various, so that diversified power-on reset controllability, which comprises but not limited to sequence controllability, duration controllability and external controllability, can be realized.

Description

technical field [0001] The invention relates to the field of FPGA technology, in particular to an FPGA device with the function of adjusting the waveform of a power-on reset signal. Background technique [0002] FPGA (Field Programmable Gate Array, Field Programmable Logic Gate Array) is a hardware programmable logic device, which is widely used in mobile communication, data center, navigation guidance and automatic driving and other fields. In the power-on stage of the FPGA, because the power supply signal cannot immediately reach the working voltage, in order to maintain the internal working state of the FPGA, a Power-On Reset (POR) circuit is usually designed inside the FPGA to generate a power-on reset pulse signal to ensure that the FPGA internal The state of the circuit is correct during the power-on process, but the circuit structure of the existing power-on reset circuit is usually fixed, and the generated power-on reset pulse signal is also fixed, and the flexibilit...

AI Technical Summary

Problems solved by technology

In the power-on stage of the FPGA, because the power supply signal cannot immediately reach the working voltage, in order to maintain the internal working state of the FPGA, a Power-On Reset (POR) circuit is usually designed inside the FPGA to generate a power-on reset pulse signal to ensure that the FPGA internal The state of the circuit is correct during the power-on process, but the circuit structure of the existing power-on reset circuit is usually fixed, and the generated power-on reset pulse signal is also fixed, and the flexibility is poor

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