Serial flash memory and address control method thereof

Abstract

The invention discloses a serial flash memory which comprises a storage array, a row decoder, a column decoder, a control module and an SPI interface. The control module further comprises an enable signal. When the last bit of the SPI row address in the SPI address signal is read, the control module enables the row enable signal, and the row enable signal enables the internal row address of the internal address of the serial flash memory to be valid and enables the row decoder to decode and select the internal row address. The invention further provides an address control method of the serialflash memory. According to the serial flash memory, the time sequence requirement on the row address can be relaxed, and the area of the row decoder can be reduced, and the area of the row driving circuit can also be reduced.

Description

technical field [0001] The invention relates to the field of semiconductor integrated circuit manufacturing, in particular to a serial flash memory. The invention also relates to an address control method of the serial flash memory. Background technique [0002] Such as figure 1 Shown is the structural diagram of the storage unit of the existing serial flash memory; figure 2 Shown is the storage layout diagram of the existing serial flash memory; such as image 3 Shown is a schematic diagram of the structure of the existing serial flash memory; Figure 4 Shown is the timing diagram of the address transmission of the existing serial flash memory during the read operation; the existing serial flash memory 201 includes: storage array 102, row decoder 204, column decoder 205, control module 203 and serial The serial peripheral interface (Serial Peripheral Interface, SPI) is the SPI interface 202 . [0003] Generally, the arrangement structure of the memory cells 101 of the...

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Problems solved by technology

[0016] Depend on Figure 4 As can be seen, in the prior art, the internal address will be valid only when the address of one word length of the SPI address signal is read. After the internal address is valid, row decoding and column decoding will be performed at the same time, and then the corresponding address can be decoded. The storage unit 101 performs operations such as reading, which requires relatively high decoding and driving requirements for rows, and will occupy a relatively large area

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