Acceleration processing method for autonomously outputting NVME protocol command

Abstract

The invention discloses an acceleration processing method for autonomously outputting an NVME protocol command. According to the method, one or more data tight coupling memory units DTCM are integrated in a CPU of an NVME subsystem; an AXI MASTER interface is added to an NVME controller, the AXI MASTER interface is accessed to an AXI bus, and an address access space is a DTCM address in a CPU; theNVME controller writes an NVME command into the DTCM through an AXI MASTER interface, and a CPU core in the NVME subsystem directly accesses the DTCM; and the NVME subsystem writes all the commands with different namespace IDs into the corresponding DTCMs according to the namespace IDs. According to the invention, the CPU reading operation frequency is reduced, the time delay is reduced, and theperformance is improved.

Description

technical field [0001] The invention relates to the field of NVME protocol command processing, in particular to an accelerated processing method for independently outputting NVME protocol commands. Background technique [0002] NVM Express (NVME): The non-volatile memory host controller interface specification is a set of interface standards mainly developed for PCIe SSD. NVME defines system interfaces, queues, registers, and command sets, and has the advantages of lower latency, better performance, and lower power consumption. [0003] In the processing flow of the existing NVME command, the first is the host stage, the host writes the NVME command to the submission queue (SubmissionQueue, SQ), and the host notifies the controller to extract the NVME command by updating the register SQ Tail Doorbell in the NVME subsystem controller; The second stage is the stage of the NVME subsystem controller. The controller extracts the NVME command from the SQ and executes the command....

AI Technical Summary

Problems solved by technology

The existing solution is that the controller gets the NVME command and writes the command into the register inside the controller, and the CPU inside the controller gets the command by reading the register, but an NVME command is 64Byte, and the data volume of a single register is only 4byte , so the CPU needs to read 16 consecutive registers to get an NVME command. This solution has the disadvantages of frequent CPU operations, long-term occupation of CPU resources, and large delay consumption.

[0004] In addition, in order to support different types of application layers, the NVME protocol supports multiple namespaces. One space can correspond to several logical spaces. Each namespace has an ID. HOST uses ID to distinguish different namespaces. Different namespaces can have different data. Structure and related settings, but while supporting multiple namespaces, it will increase the processing overhead and design difficulty of the software for different namespaces

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