NVME protocol command acceleration processing system

Abstract

The invention discloses an NVME protocol command acceleration processing system. The system comprises an NVME controller, a command processing module and a CPU which are arranged in an NVME subsystem,the command processing module comprises a command storage SRAM and a bus protocol conversion module. The command storage SRAM is connected with the NVME controller through an RAM bus and used for receiving a host command from the NVME controller, and the bus protocol conversion module converts the RAM bus into an AXI bus, so that the CPU reads the host command to be executed in the command storage SRAM through the AXI bus; the command storage SRAM is implemented in a queue manner, the NVME controller submits a host command to the queue by using a Tail entry pointer, and the CPU obtains the host command from the queue by using a Head entry pointer. According to the invention, the CPU reading operation frequency can be reduced, the time delay is reduced, and the performance is improved.

Description

technical field [0001] The invention relates to an NVME protocol command acceleration processing system, which belongs to the technical field of storage. Background technique [0002] NVM Express (NVME): The non-volatile memory host controller interface specification is a set of interface standards mainly developed for PCIe SSD. NVME defines system interfaces, queues, registers, and command sets, and has the advantages of lower latency, better performance, and lower power consumption. [0003] In the processing flow of the existing NVME command, the first is the host stage, the host writes the NVME command to the submission queue (SubmissionQueue, SQ), and the host notifies the controller to extract the NVME command by updating the register SQ Tail Doorbell in the NVME subsystem controller; The second stage is the stage of the NVME subsystem controller. The controller extracts the NVME command from the SQ and executes the command. After executing the command, it writes the ...

AI Technical Summary

Problems solved by technology

The existing solution is that the controller gets the NVME command and writes the command into the register inside the controller, and the CPU inside the controller gets the command by reading the register, but an NVME command is 64Byte, and the data volume of a single register is only 4byte , so the CPU needs to read 16 consecutive registers to get an NVME command. This solution has the disadvantages of frequent CPU operations, long-term occupation of CPU resources, and large delay consumption.

Moreover, the existing command execution method is polling, which has the problem of command response delay. On the one hand, it does not respond to the management commands sent by HOST in time, and on the other hand, it reduces the read and write performance.

Images