Chip-on-film packaging structure
A technology of film-on-chip packaging and pins, which is applied in the direction of electrical components, electric solid devices, circuits, etc., can solve problems such as increased risk, machine precision error, and difficulty in providing safe space or buffer space, so as to reduce risks and improve The effect of manufacturing yield
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[0053] Figure 1A is a schematic top view of a chip-on-film packaging structure according to an embodiment of the present invention. Figure 1B yes Figure 1A An enlarged schematic view of region A of . Figure 1C yes Figure 1B Schematic cross-sectional view along section line B-B'. In order to clearly show the connection relationship between the pin 120, the chip 130 and the bump 140, Figure 1A The chip 130 and the solder resist layer 150 are shown in perspective, and the encapsulant 160 is omitted.
[0054] Please refer to Figure 1A to Figure 1C , in this embodiment, the film-on-chip packaging structure 100 includes a flexible substrate 110, a plurality of pins 120, a chip 130, and a plurality of bumps 140, wherein the flexible substrate 110 can be made of polyethylene p-phenylene Diformate (polyethylene terephthalate, PET), polyimide (Polyimide, PI), polyethersulfone (PES), polycarbonate (polycarbonate, PC) or other suitable flexible materials. On the other hand, the...
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