Semiconductor structure and manufacturing method thereof, semiconductor device and chip

Abstract

The invention provides a semiconductor structure and a manufacturing method thereof, a semiconductor device and a chip. The semiconductor structure comprises a semiconductor substrate and a dielectriclayer on the semiconductor substrate, a via hole in the dielectric layer, a metal interconnection line formed in the via hole, and a cobalt-containing capping layer on the metal interconnection line.The manufacturing method of the semiconductor structure comprises the steps that a semiconductor substrate and a dielectric layer on the semiconductor substrate are provided, and a via hole is formedin the dielectric layer; metal is deposited in the via hole to form a metal interconnection line; the metal interconnection line is ground to a position below the surface of the dielectric layer; a cobalt-containing capping layer is selectively deposited over the metal interconnection line such that the cobalt-containing capping layer is over the metal interconnection line. The cobalt-containingcovering layer is selectively formed on the metal interconnection line, stress migration and electromigration are loaded by the cobalt-containing covering layer, charges in the metal interconnection line are effectively prevented from being migrated into the dielectric layer, the situation that the metal interconnection line is damaged due to stress migration or electromigration is reduced, and the reliability of the device is improved.

Description

technical field [0001] The disclosure belongs to the technical field of semiconductors, and in particular relates to a semiconductor structure and a manufacturing method thereof, a semiconductor device, and a chip. Background technique [0002] In the subsequent process of the semiconductor device, it is necessary to form a metal interconnection layer on the semiconductor device. Each layer of metal interconnection layer includes a metal interconnection line and a dielectric layer. It is necessary to form a via hole in the dielectric layer. In the via hole Metal is deposited to form metal interconnect lines. [0003] Affected by factors such as environmental pressure in the manufacturing process and voltage in the working process, there will be certain stress migration (Stress migration, SM) and electro-migration (Electro-migration, EM) in the metal interconnection. Especially as the integration of semiconductors becomes higher and higher, the size of metal interconnects be...

AI Technical Summary

Problems solved by technology

Especially as the integration of semiconductors becomes higher and higher, the size of metal interconnects becomes smaller. The smaller the size, the greater the impact of stress migration and electromigration of metal interconnects on the performance of semiconductor devices. Even cause semiconductor devices to fail

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