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GPU-based rule SCMA high-speed parallel decoding method

A decoding and rule technology, applied in the field of communication, can solve the problem of high complexity of SCMA decoding, achieve the effect of optimizing efficiency, reducing startup overhead, and small synchronization overhead

Active Publication Date: 2020-11-20
HANGZHOU INNOVATION RES INST OF BEIJING UNIV OF AERONAUTICS & ASTRONAUTICS
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  • Claims
  • Application Information

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Problems solved by technology

[0004] The purpose of the present invention is to provide a GPU-based regular SCMA high-speed parallel decoding method to solve the problem of high SCMA decoding complexity in the prior art, and to utilize the parallel core resources of the GPU to improve computational efficiency

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  • GPU-based rule SCMA high-speed parallel decoding method
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  • GPU-based rule SCMA high-speed parallel decoding method

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Embodiment Construction

[0027] The present invention will be described in detail below in conjunction with the accompanying drawings.

[0028] The present invention provides a kind of GPU-based rule SCMA high-speed parallel decoding method, what adopt is based on factor graph (such as figure 1 Shown) logarithmic domain iterative decoding algorithm. The decoding method includes three stages: an initialization stage, a decoding and judgment stage, and a result return stage. The initialization stage includes the following steps 1 and 2. The decoding and judgment stage includes the following steps 3 to 5. The following step 6 is the result return stage. The entire decoding process is as follows: figure 2 As shown, the details are as follows:

[0029] Step 1: Host initialization. Including allocating memory space for codebook information, codebook factor map information, signal received by the receiver, channel state information, decoding decision result, namely log likelihood ratio of source bits (st...

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Abstract

The invention discloses a GPU-based rule SCMA high-speed parallel decoding method. The decoding process can be divided into three stages: an initialization stage, a decoding and judgment stage and a result return stage. The initialization stage comprises the following steps 1 and 2, the decoding and judgment stage comprises the following steps 3-5, and the following step 6 is a result return stage; the decoding method provided by the invention comprises two levels of parallelism. The first level is parallelism between thread blocks, the thread blocks and the data blocks are in one-to-one correspondence, and each thread block can independently run in parallel. the second level is the parallelism among the threads in the thread block. The method is high in calculation efficiency and low in synchronization overhead. According to the GPU memory allocation method used by the invention, the optimal balance between the memory access efficiency and the space requirement is obtained according to the characteristics of access speed and capacity existing in the global memory and the shared memory, the access locality is good, and the memory access and storage efficiency is optimized.

Description

technical field [0001] The invention belongs to the technical field of communication, and relates to a regular SCMA high-speed parallel decoding method based on a GPU (Graphics Processing Unit, graphics processor). Background technique [0002] In order to realize the "Internet of Everything", the future wireless communication system needs to support the connection of a large number of terminals. For this reason, various non-orthogonal multiple access technologies, especially sparse code division multiple access (SCMA, Spare Code Multiple Access) have attracted the attention of academic and industrial circles. SCMA includes regular SCMA and irregular SCMA. Among them, regular SCMA has a simple structure and can provide more than three times the number of connections compared with orthogonal multiple access. Organizations submitted proposals to rule SCMA. However, the decoding complexity of SCMA (including regular SCMA and irregular SCMA) is very high, even if an approximat...

Claims

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Application Information

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IPC IPC(8): G06F9/38G06F9/50G06F9/54H04L1/00H03M13/29
CPCG06F9/38G06F9/5016G06F9/544H04L1/005H03M13/2948
Inventor 李舒韩玉玺
Owner HANGZHOU INNOVATION RES INST OF BEIJING UNIV OF AERONAUTICS & ASTRONAUTICS