Scheduling method and device for out-of-order execution queue in out-of-order processor

Abstract

The invention discloses a scheduling method and device for an out-of-order execution queue in an out-of-order processor. The method comprises the following steps: constructing a sequence maintenance queue with the same number of items as the out-of-order execution queue, and distributing empty items for an instruction and data entering the out-of-order execution queue, and the sequence maintenancequeue comprises an recognition id domain; numbering the out-of-order execution queues of the multiple items in sequence, and recording id numbers of the out-of-order execution queues through id domains of the sequence maintenance queues; enabling the instruction to enter an out-of-order execution queue item pointed by an id number corresponding to a tail pointer of the order maintenance queue; and instruction execution of the prepared items is selected from the out-of-order execution queue according to the id number information given by the sequence maintenance queue. According to the embodiment of the invention, the out-of-order execution queue sequence can be maintained by using the sequence maintenance queue so as to improve the scheduling efficiency, reduce the scheduling complexity,realize low power consumption and low delay and save the area, thereby improving the performance of the processor, improving the dominant frequency, reducing the power consumption and reducing the cost.

Description

Technical field [0001] Technical Field The present invention relates to microprocessors, and particularly to a scrambled order execution processor queue scheduling method and apparatus. Background technique [0002] Scrambled order execution processors queue to cache a certain number of instructions (a program instruction may be an instruction, the processor may be decoded into the interior of the internal operation, an instruction may be translated into a translated into multiple operations may operations) and data, responsible for entering instructions and data distribution queue empty entry, would be consistent with the data and instructions that perform certain condition is selected from the queue. Scrambled instruction processor to execute instructions out of order in the queue, it will not flow in the processor in the order specified in the program, as long as the execution condition is satisfied, subsequent instructions can be executed across the front of the first, to inc...

AI Technical Summary

Problems solved by technology

One method is to record the age of each instruction entering the out-of-order execution queue in the out-of-order execution queue, that is, use the counter method, and then sort according to the counter. The disadvantage is that the counter records need to add additional registers, and the registers will overflow. Moreover, the delay of multi-level comparison and selection of the sorting circuit is also very large.

Another commonly used method is to use the order of instructions in the processor recorded in ROB (Reorder Buffer) to sort, and use the position of each instruction in ROB as the age information of the instruction. The problem with this is that ROB In essence, it is a FIFO (First Input First Output, first in, first out) queue. The age information cannot be expressed by directly using its address. It needs to be transformed, and there is also the problem of multi-level comparison circuits.

Another method is to use pointers to maintain the order of the out-of-order execution queue. The problem is that after each instruction and data are selected for execution, a large number of data movements between registers are required to maintain the order, which consumes a lot of power.

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