YOLO V3 and YOLO V3 Tiny network switching method based on FPGA (Field Programmable Gate Array)

Abstract

The invention discloses a YOLO V3 and YOLO V3 Tiny network switching method based on an FPGA (Field Programmable Gate Array). According to the invention, on the premise of not increasing extra controllogic, data is controlled to pass through or skip the functional modules by configuring parameters; parameter control is operated or standby according to a preset YOLO _ V3 network structure; meanwhile, the parameters can also be configured into a YOLO V3 Tiny3 network structure, so that the effect of switching networks can be achieved through the design, the selection of the networks can be dynamically adjusted as required, and the requirements for higher precision, higher speed and lower power consumption are met.

Description

technical field [0001] The invention relates to the technical field of network switching methods, in particular to an FPGA-based YOLO V3 and YOLO V3Tiny network switching method. Background technique [0002] With the continuous popularization of artificial intelligence technology, its application in all walks of life is becoming more and more extensive, but the target detection based on FPGA, although benefiting from the high-speed calculation and low power consumption of FPGA, is also limited by its hardware Features, limited resources can only accommodate network models with limited equivalents, so it causes an embarrassing problem. Under FPGA, the network accuracy of YOLO V3 is about 10% to 15% higher than that of YOLO V3 Tiny, but under FPGA-based YOLO V3 The frame rate of the network is only 1.836FPS, and YOLO V3 Tiny has 26.141FPS in the same environment. However, under the common requirements of precision and speed, one FPGA development board cannot accommodate two n...

AI Technical Summary

Problems solved by technology

[0002] With the continuous popularization of artificial intelligence technology, its application in all walks of life is becoming more and more extensive, but the target detection based on FPGA, although benefiting from the high-speed calculation and low power consumption of FPGA, is also limited by its hardware Features, limited resources can only accommodate network models with limited equivalents, so it causes an embarrassing problem. Under FPGA, the network accuracy of YOLO V3 is about 10% to 15% higher than that of YOLO V3 Tiny, but under FPGA-based YOLO V3 The frame rate of the network is only 1.836FPS, and YOLO V3 Tiny has 26.141FPS in the same environment. However, under the common requirements of precision and speed, an FPGA development board cannot accommodate two network structures.

[0003] Schematic diagram of the structure of the YOLO model under the traditional FPGA figure 1 As shown, the main convolution module consists of N_PE computing units. Through the AXI bus, the weights are cached to the FPGA, and these convolution units perform calculations and other operations at the same time, and then write the results into the cache. This design structure is simple and direct , but when the logic design is completed, the shape of the network has been determined, subsequent data can only flow according to the current design, and the network loses its variability.

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