Laterally diffused transistor and manufacturing method thereof

Abstract

The invention discloses a lateral double-diffused transistor and a manufacturing method thereof. The lateral double-diffused transistor comprises a substrate, a drift region, a drain region, a body region, a source region, a body contact region and a gate structure, wherein the drift region is positioned on the upper surface of the substrate; the drain region is positioned at one end of the upperpart of the drift region; the body region is positioned at the other end; the source region and the body contact region are positioned at the upper part of the body region and are sequentially arranged from inside to outside; and the gate structure is located on the upper surface of the body region and extends to at least one part of the upper surface of the drift region, and the body contact region is arranged in the body region in a manner that the bottom is deeper than the bottom of the source region, so that the self-protection capability of the lateral diffusion transistor is enhanced.

Description

technical field [0001] The present invention relates to the technical field of semiconductors, in particular to a lateral diffusion transistor and a manufacturing method thereof. Background technique [0002] As a kind of power semiconductor device, laterally-diffused metal-oxide semiconductor (LDMOS for short) is characterized in that it has a drift region inside to share the reverse voltage, so it has excellent withstand voltage characteristics. [0003] figure 1 shows a common LDMOS device in the prior art, refer to figure 1 The specific structure of the LDMOS device is described as follows: the LDMOS device 100 belongs to an N-type LDMOS device, which includes a P-type substrate 1 and an N-type drift region 2 located on the upper surface of the substrate 1, and one end of the upper part of the drift region 2 has an N+ Type drain region 3 and the other end has a P-type body region 4, the top of the body region 4 is successively provided with an N+ type source region 5 a...

AI Technical Summary

Problems solved by technology

[0004] However, since LDMOS devices are usually used in the case of high current and high voltage, so figure 1 When the shown LDMOS device 100 is turned on, more holes (that is, majority carriers) will flow from the body region 4 to the body contact region 6 along the direction of the solid arrow shown in the figure, so that the body region 4 will There is a phenomenon that the potential is raised, which may cause the parasitic NPN in the drift region 2-body region 4-source region 5 to be turned on by mistake

After the parasitic NPN is falsely turned on, a current path is formed from the drain region 3 through the parasitic channel to the source region 5 via the dotted line arrow, that is, the conduction from the drain region 3 to the source region 5 is not controlled by the gate-source voltage, so that the device function failure

Images