Power consumption attack resisting method based on cyclic shift of bit permutation and fixed permutation table

Abstract

The invention discloses a power consumption attack resisting method based on cyclic shift of bit permutation and a fixed permutation table, which comprises the following steps of: inputting a plaintext, and after a round of calculation is finished, performing bit permutation on an intermediate value and storing the intermediate value into a register; and before the next round of calculation is started, performing bit permutation recovery operation, so that the intermediate value is recovered to the original sequence, and subsequent calculation is carried out. The bit permutation comprises a cyclic shift mode and a fixed permutation table mode. In the cyclic shift scheme, the control signals of the bit permutation module and the bit permutation recovery module are the same, so that one module can be shared, and half of resource overhead is saved. In the scheme of the fixed permutation table, inverse transformation of the fixed permutation table is the fixed permutation table, namely, the original sequence can be recovered through two times of same transformation, resources can be repeatedly utilized, and extra area expenditure is reduced. And meanwhile, the positions of the ith timeand the (i+1)th time are completely staggered, so that for the registers at the same position, the data of two adjacent times relate to all 16 bytes in the past, and the data confusion degree is increased to the maximum.

Description

technical field [0001] The invention relates to the field of cryptographic algorithms, in particular to a power consumption attack resistance method based on bit permutation cyclic shift and fixed permutation table. Background technique [0002] For hardware-implemented cryptographic algorithm schemes, the attacker's focus is often on the operation of writing intermediate values ​​into registers. In this operation, the energy consumption of the cryptographic device will vary according to the flipping of the register. Therefore, if the data writing process can be confused, the anti-power consumption attack capability of the cryptographic device can be improved to a certain extent. [0003] The anti-power consumption attack scheme based on register randomization divides the data into 4 groups after the calculation is completed, and then randomly stores them in 4 registers, and restores the intermediate value data to the normal order before the next round of calculation. This ...

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Problems solved by technology

Therefore, the improved power consumption attack resistance of this scheme is small. In addition, certain combinational logic will be added before and after the register, which will affect the performance of the cryptographic device.

[0004] An anti-power attack scheme based on dynamic intermediate value storage. Taking the DES algorithm as an example, the introduction adds a pair of registers. During the calculation process, the calculated intermediate value will be alternately stored in the two pairs of registers, so that the corresponding The intermediate values ​​of the two adjacent calculations are stored in different pairs of registers to improve the power consumption attack resistance of the cryptographic device, but this solution will double the register consumption

[0005] An anti-power consumption attack scheme based on 4-bit replacement, which divides a byte into high 4 bits and low 4 bits, and then replaces them respectively according to the replacement table. After the replacement table is used, it will be updated according to the random number. Although the scheme can increase the attack difficulty to a certain extent, it consumes a large additional area

[0006] Although the above scheme can improve the power consumption attack resistance of the cryptographic equipment to a certain extent, on the one hand, the enhanced power consumption attack resistance is limited; , but also requires additional resource consumption, that is, the construction of the random number generator

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