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Capacitor array logic control method in successive approximation analog-to-digital converter

An analog-to-digital converter and capacitor array technology, applied in the field of capacitor array logic control, can solve problems such as capacitor mismatch and poor performance

Active Publication Date: 2020-12-04
重庆中易智芯科技有限责任公司
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  • Abstract
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  • Application Information

AI Technical Summary

Problems solved by technology

The existing switch logic control methods hardly have a good performance in solving the problem of capacitance mismatch. Therefore, the present invention makes improvements to this part

Method used

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  • Capacitor array logic control method in successive approximation analog-to-digital converter
  • Capacitor array logic control method in successive approximation analog-to-digital converter
  • Capacitor array logic control method in successive approximation analog-to-digital converter

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Embodiment Construction

[0020] The technical solutions in the embodiments of the present invention will be described clearly and in detail below with reference to the drawings in the embodiments of the present invention. The described embodiments are only some of the embodiments of the invention.

[0021] This example will show that the capacitor array logic control method of the present invention is used on a differential segment capacitive successive approximation analog-to-digital converter of lower plate sampling, such as Figure 5 , and describe in detail how it works.

[0022] The capacitor array is a two-segment type, specifically 8+7+1, 8 bits in the LSB (low order) segment, 7 bits in the MSB (high order) segment plus a redundant capacitor. Let the unit capacitance be C, and the LSB section capacitance be C, 2C, ..., 2 7 C, while the MSB segment is C, 2C, ..., 2 6 C and a redundant capacitor C. The segmented capacitor array greatly reduces the required total capacitor size and effectively s...

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Abstract

The invention discloses a capacitor array logic control method in a successive approximation analog-to-digital converter, and belongs to the technical field of an analog integrated circuit design. Themethod is a design method of switching logic of a differential capacitor array. According to the method, a capacitor array can access and use the least capacitors in each judgment so that the least non-ideal factors such as mismatch are introduced. Compared with a traditional method and numerous power consumption improvement methods, the method has the advantages that under the condition that thebasic structure of the successive approximation analog-to-digital conversion circuit is not modified, linearity of the successive approximation analog-to-digital converter is improved, and main performance parameters such as an SNDR (Signal to Noise Distortion Ratio) and an SFDR (Dynamic Range) are obviously improved; and subsequent analog or digital calibration of the high-order high-precision successive approximation analog-to-digital converter is facilitated so that overall performance of the converter is improved. Moreover, the method has universality and is suitable for the successive approximation analog-to-digital conversion circuits of most differential capacitor array structures.

Description

technical field [0001] The invention belongs to the technical field of analog integrated circuits, and in particular relates to a capacitor array logic control technology of a differential capacitive successive approximation analog-to-digital converter. Background technique [0002] Capacitive DAC is currently the most important design solution for successive approximation analog-to-digital converters. Among them, the manufacturing accuracy and matching degree of the semiconductor process of the capacitor are the most important factors affecting the accuracy of the analog-to-digital converter circuit. In the actual manufactured analog-to-digital converter circuit, due to the influence of parasitic capacitance and the limitation of semiconductor manufacturing process technology, the capacitance value of the actually produced capacitor cannot be the ideal capacitance value envisioned in the design, and the capacitance of each bit It is impossible to perfectly match the binary...

Claims

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Application Information

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IPC IPC(8): H03M1/38H03M1/08
CPCH03M1/38H03M1/08
Inventor 王巍丁立樊琦赵汝法袁军霍军黎淼张祯
Owner 重庆中易智芯科技有限责任公司
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