A method and device for reducing high temperature off-state leakage of semiconductor devices

Abstract

The present invention provides a method and device for reducing high-temperature off-state leakage of a semiconductor device. The method includes: for a target device, acquiring a first temperature transfer characteristic curve of the target device at room temperature and a second temperature transfer curve of the target device at the target temperature characteristic curve; obtain the first gate voltage corresponding to the sub-threshold leakage cut-off current of the target device, the first threshold voltage and the second gate voltage corresponding to the sub-threshold leakage cut-off current; determine the target threshold voltage of the target device at the target temperature; based on the target The threshold voltage adjusts the trap ion implantation concentration of the target device; in this way, the target threshold voltage can be achieved only by implanting ions based on the adjusted ion implantation concentration; on the temperature transfer characteristic curve, it is ensured that the cutoff point of the subthreshold leakage cutoff current falls on the gate The voltage is zero, so that the off-state leakage can be minimized at the high temperature of the device without making major changes to the device structure and process flow, and the cost is guaranteed.

Description

technical field [0001] The invention belongs to the technical field of semiconductor devices, and in particular relates to a method and device for reducing high-temperature off-state leakage of semiconductor devices. Background technique [0002] Silicon-based CMOS technology is currently the mainstream technology for high-temperature integrated circuit design. However, with the reduction of threshold voltage, channel length and gate oxide thickness, high leakage current is becoming the main factor affecting high temperature CMOS circuits, resulting in increased static power consumption of high temperature integrated circuits. [0003] The main characteristics of MOS devices under high temperature conditions are the increase of leakage current and the drift of threshold voltage. Although the static power consumption of high-temperature integrated circuits can be reduced by reducing the leakage of the PN junction within the device and improving the isolation between the devi...

AI Technical Summary

Problems solved by technology

[0005] Aiming at the problems existing in the prior art, the embodiment of the present invention provides a method and device for reducing the high-temperature off-state leakage of semiconductor devices, which is used to solve the problem of reducing the high-temperature off-state leakage of the device in the prior art, which needs to be optimized for the device structure and Substantial changes in the process flow, leading to technical problems with complex process flow and high cost

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