Method and device for reducing high-temperature off-state electric leakage of semiconductor device

Abstract

The invention provides a method and device for reducing high-temperature off-state electric leakage of a semiconductor device, and the method comprises the steps: obtaining a first temperature transfer characteristic curve of a target device at a normal temperature and a second temperature transfer characteristic curve of the target device at a target temperature for the target device; obtaining afirst gate voltage and a first threshold voltage corresponding to the sub-threshold leakage cut-off current of the target device and a second gate voltage corresponding to the sub-threshold leakage cut-off current; determining a target threshold voltage of the target device at the target temperature; and adjusting the trap ion implantation concentration of the target device based on the target threshold voltage. In this way, the target threshold voltage is achieved only by injecting ions based on the adjusted ion injection concentration. On a temperature transfer characteristic curve, a cut-off point of the sub-threshold leakage cut-off current is ensured to fall at a position where the gate voltage is zero, so that the off-state electric leakage of the device at high temperature can be ensured to reach the minimum without greatly changing the structure and the process flow of the device, and the cost is reduced.

Description

technical field [0001] The invention belongs to the technical field of semiconductor devices, and in particular relates to a method and a device for reducing high-temperature off-state leakage of semiconductor devices. Background technique [0002] Silicon-based CMOS technology is currently the mainstream technology for high-temperature integrated circuit design. However, with the reduction of threshold voltage, channel length and gate oxide thickness, high leakage current is becoming the main factor affecting high-temperature CMOS circuits, resulting in increased static power consumption of high-temperature integrated circuits. [0003] The main characteristics of MOS devices under high temperature conditions are the increase of leakage current and the drift of threshold voltage. Although the static power consumption of high-temperature integrated circuits can be reduced by reducing the internal PN junction leakage of the device and improving the isolation between devices;...

AI Technical Summary

Problems solved by technology

[0005] Aiming at the problems existing in the prior art, the embodiment of the present invention provides a method and device for reducing the high-temperature off-state leakage of semiconductor devices, which is used to solve the problem of reducing the high-temperature off-state leakage of the device in the prior art, which needs to be optimized for the device structure and Substantial changes in the process flow, leading to technical problems with complex process flow and high cost

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