A shift register has a plurality of stages driven by first, second, and third clock signals. Each stage includes a first transistor coupled between a first power source and an output node, and having a gate electrode coupled to a first node, a second transistor coupled between the output node and the third input line, and having a gate electrode coupled to a second node, a third transistor coupled between the first power source and the first node, and having a gate electrode coupled to an input terminal receiving the start pulse or an output signal of a previous stage, a fourth transistor coupled between the first node and a second power source, and having a gate electrode coupled to the first input line, and a fifth transistor coupled between the input terminal and the second node, and having a gate electrode coupled to the second input line.