Three-dimensional memory structure, manufacturing method thereof and three-dimensional memory device

A memory, three-dimensional technology, applied in the direction of electric solid-state devices, semiconductor devices, electrical components, etc., can solve problems such as uneven stress distribution, low storage capacity, unstable structure of three-dimensional memory devices, etc., to achieve improved stability and uniform stress distribution Effect

Pending Publication Date: 2020-12-08
YANGTZE MEMORY TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide a three-dimensional memory structure, which is used to solve the problem of structural instability and low storage capacity of three-dimensional memory devices in the prior art due to uneven stress distribution. question

Method used

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  • Three-dimensional memory structure, manufacturing method thereof and three-dimensional memory device
  • Three-dimensional memory structure, manufacturing method thereof and three-dimensional memory device
  • Three-dimensional memory structure, manufacturing method thereof and three-dimensional memory device

Examples

Experimental program
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Embodiment 1

[0068] Figure 7 A top view of the three-dimensional memory structure 100 of this embodiment is shown, Figure 8 shown in Figure 7 The top view of the three-dimensional memory structure 100 after forming the gate spacer 1 and the bit line 2, please refer to Figure 7 , the three-dimensional memory structure 100 includes a substrate (not shown) and a stack structure, and the stack structure is formed on the substrate.

[0069] In this embodiment, the three-dimensional memory structure 100 includes a substrate at the bottom, such as a semiconductor substrate, the substrate can be selected according to the actual requirements of the device, and the substrate can include a silicon substrate , germanium (Ge) substrate, silicon germanium (SiGe) substrate, SOI (Silicon-on-insulator, silicon-on-insulator) substrate or GOI (Germanium-on-Insulator, germanium-on-insulator) substrate, etc., in In other embodiments, the substrate can also be a substrate including other elemental semico...

Embodiment 2

[0078] Figure 9 A top view of the three-dimensional memory structure 200 of this embodiment is shown, Figure 10 shown in Figure 9 The top view of the three-dimensional memory structure 200 after forming the gate spacer 1 and the bit line 2, please refer to Figure 9 and Figure 10 , the three-dimensional memory structure 200 includes a substrate (not shown) and a stack structure, and the stack structure is formed on the substrate. The difference between the present embodiment and the first embodiment is that a gate wall structure 3 is provided in the step area of ​​each partition, and other structures are the same as those of the first embodiment, so repeated descriptions will not be repeated. see Figure 9 , the gate wall structure 3 extends from an end of the step area away from the core array area to an end close to the core array area, and the gate wall structure 3 is a partial stack that is completely preserved during the process of forming steps by an etching trim...

Embodiment 3

[0081] Figure 11 A top view of the three-dimensional memory structure 300 of this embodiment is shown, Figure 12 shown in Figure 11 For the top view of the three-dimensional memory structure 300 in which the gate spacer 1 and the bit line 2 are formed, please refer to Figure 11 , the three-dimensional memory structure 300 includes a substrate (not shown) and a stack structure, and the stack structure is formed on the substrate. The difference between the present embodiment and the first embodiment lies in that the relative positions of the step area and the core array area in each subregion are different, and other structures are the same as those of the first embodiment, so no repeated description is given. see Figure 11 , in this embodiment, the first stepped area S1 is arranged on the side (lower side) of the first subregion A1 close to the third subregion A3; the second stepped region S2 is arranged on the second subregion A3 The side (left side) of the second sub...

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Abstract

The invention provides a three-dimensional memory structure. The three-dimensional memory structure comprises a substrate; and a stacking structure which is formed on the substrate, and the stacking structure is provided with a first subarea and a second subarea which are sequentially arranged in the first direction; wherein the first subarea comprises a first core array area and a first step areawhich are sequentially arranged in the second direction, the first step area is located on the edge of the first subarea, and the second subarea comprises a second core array area and a second step area which are sequentially arranged in the first direction; the second step area is located at the edge of the second subarea, and the first direction intersects with the second direction. By utilizing the method, the stress after the etching of gate isolation grooves in the three-dimensional memory can be balanced, and the stress after increasing of the number of layers of the gate laminated structure of the three-dimensional memory can be balanced, so that the stress distribution is more uniform, and the stability of the structure of the three-dimensional memory is improved.

Description

technical field [0001] The invention belongs to the technical field of semiconductor integrated circuits, and relates to a three-dimensional memory structure, a manufacturing method thereof and a three-dimensional memory device. Background technique [0002] In the chip manufacturing process, the silicon substrate (Si Substrate) is used as the carrier for making the chip. As the number of chip layers increases, more dielectric films (such as tetraethoxysilane (TEOS), nitrogen, etc.) need to be used. titanium oxide (SIN), polysilicon (POLY)). Taking 3D NAND as an example, the step region, channel structure, and gate gap region (GLArea) in 3D NAND need to be filled with more dielectric, and at the same time, the film structure will become complicated, and the After the annealing treatment, the film will be deformed, and the silicon substrate is difficult to support the deformation of the wafer (Wafer) caused by the stress of the film, which will eventually lead to arcing defo...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L27/11519H01L27/11524H01L27/11529H01L27/11551H01L27/11565H01L27/1157H01L27/11573H01L27/11578
CPCH10B41/10H10B41/41H10B41/20H10B41/35H10B43/10H10B43/20H10B43/40H10B43/35
Inventor 张坤周文犀
Owner YANGTZE MEMORY TECH CO LTD
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