Time sequence analysis method and device based on EDA tool, and storage medium

Abstract

Embodiments of the invention disclose a time sequence analysis method and device based on an EDA tool, and a storage medium. The method comprises the steps of acquiring a pre-configuration library file, a gate-level netlist and a time sequence constraint corresponding to a to-be-designed chip; carrying out layout wiring processing according to the pre-configuration library file, the gate-level netlist and the time sequence constraint to obtain an initially designed circuit; performing voltage drop analysis processing on the initially designed circuit to obtain a first voltage drop analysis result; if the first voltage drop analysis result shows that a first voltage drop violation unit exists in the initially designed circuit, acquiring a first voltage drop value corresponding to the firstvoltage drop violation unit; performing sequential analysis processing on the first voltage drop violation unit according to the first voltage drop value to obtain a first delay change value corresponding to the first voltage drop violation unit; and generating a target time sequence analysis report corresponding to the initially designed circuit based on the first delay change value, wherein thetarget time sequence analysis report is used for realizing time sequence repair processing of the initially designed circuit.

Description

technical field [0001] The invention relates to the technical field of integrated circuits, in particular to a timing analysis method, device and storage medium based on an EDA tool. Background technique [0002] Currently, all chips must undergo chip delivery verification after the design is completed, that is, verification based on a specific operating voltage to ensure that the chip functions meet the expected requirements. If the voltage drop (IR-Drop) of the power supply network in the actual operation of the chip does not meet the voltage range when the chip is delivered and verified, it indicates that the chip cannot work normally. [0003] In view of the above problems, in the related art, the problems existing in the design are repaired through continuous iteration of the Engineering Change Order (Engineer Changing Order, ECO) process. Specifically, these excessive IR-Drop points in the chip circuit are often repaired by analyzing and adjusting the power supply net...

AI Technical Summary

Problems solved by technology

[0004] The embodiment of the present application provides a timing analysis method, device, and storage medium based on EDA tools, which effectively overcomes the defect that the IR-Drop violation area cannot be repaired due to excessive layout and wiring density, improves chip design efficiency, and further Ensure the correctness of the chip function

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