Method for detecting highest temperature in three-dimensional integrated circuit layer based on Fermat point model
An integrated circuit, maximum temperature technology, applied in CAD circuit design, climate sustainability, design optimization/simulation, etc. Overcome the effects of taking too long
Active Publication Date: 2020-12-18
XIDIAN UNIV
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[0006] The purpose of the present invention is to address the deficiencies of the above-mentioned prior art, and propose a method for detecting the maximum temperature in a three-dimensional integrated circuit layer based on the Fermat point model, which is used to solve the problem that the maximum temperature detection in a three-dimensional integrated circuit layer takes a long time and detects There are limitations in the scope of application of the method
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[0036] The present invention will be described in further detail below in conjunction with the accompanying drawings.
[0037] refer to figure 1 , to further describe in detail the specific steps for realizing the present invention.
[0038] Step 1, dividing the silicon layer in the three-dimensional integrated circuit.
[0039] The constructed three-dimensional integrated circuit physical model is as follows figure 2 , figure 2It is composed of n silicon layers stacked in the vertical direction. The silicon layer in a three-dimensional integrated circuit is composed of an interconnection layer, a silicon layer, and an insulating layer from top to bottom. The insulating layer connects the silicon base layer of the upper layer and the interconnection layer of the next layer. , L represents the length of the silicon layer in the three-dimensional integrated circuit, W represents the width of the silicon layer in the three-dimensional integrated circuit, where the side view ...
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The invention discloses a method for detecting the highest temperature in a three-dimensional integrated circuit layer based on a Fermat point model, which mainly solves the problems of incapability of quickly detecting the highest temperature in a silicon layer, low applicability of the detection method and the like in the prior art, and comprises the following steps of: (1) dividing the siliconlayer in a three-dimensional integrated circuit; (2) calculating the temperature rise of each grid node in the silicon layer; (3) calculating the temperature of each grid node of multiple heat sourcesin the silicon layer; (4) calculating geometric Fermat points corresponding to three heat source positions in the layer; and (5) detecting the highest temperature in the three-dimensional integratedcircuit layer. According to the method, the temperatures of the grid nodes at all moments in the silicon layer can be rapidly solved, the highest temperature in the three-dimensional integrated circuit layer is detected, the consumed time is short, and the applicability is high.
Description
technical field [0001] The invention belongs to the technical field of electronic circuits, and further relates to a method for detecting the maximum temperature in a layer of a three-dimensional integrated circuit based on a Fermat point model in the technical field of electronic devices. The invention can be used to quickly detect the highest temperature in the three-dimensional integrated circuit layer, and provide reference for the thermal management design scheme of the three-dimensional integrated circuit. Background technique [0002] A three-dimensional integrated circuit stacks and interconnects multiple chips in a vertical direction through thermal silicon vias (TSV for short), so as to obtain better electrical performance. Compared with traditional integrated circuits, TSV can realize vertical interconnection and communication between layers, effectively shortening the length of interconnection lines, reducing delay and power consumption. With the shrinking of th...
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Login to View More IPC IPC(8): G06F30/39G06F30/23G06F119/08
CPCG06F30/39G06F30/23G06F2119/08Y02D10/00
Inventor 董刚宋栋梁朱樟明杨银堂
Owner XIDIAN UNIV