Systems and methods for performing dynamic on-chip calibration of memory control signals

Abstract

The application relates to systems and methods for performing dynamic on-chip calibration of memory control signals. Systems and methods of dynamically calibrating memory control signals during increase of wordline voltage for memory technologies subject to charge loss are disclosed. In one aspect, an exemplary method may comprise using an internal node, such as a wordline regulator output or return feedback line or a replica of the wordline, as proxy for the local wordline voltage. In one or more further embodiments, the proxy signal may be converted to digital signal or code and even determined in the background before the signal is needed for calibration. As a function of the disclosed technology, calibration of memory control signals, such as pass voltage and wordline read-verify voltage, may be performed during increase of the wordlines voltage with no impact or penalty on read / program time.

Description

technical field [0001] The present disclosure relates generally to multi-level flash memory control, and more particularly to on-chip systems and methods for performing improved calibration of memory control signals. Background technique [0002] Various modern semiconductor memories, such as three-dimensional NAND flash memory, may suffer from early retention in the lateral direction (ie, rapid exponential charge depletion over time from a programming event) due to shared charge trapping layers. Figures 1A to 1B is a diagram illustrating a three-dimensional NAND flash memory known in the art. Such as Figure 1A As shown in , a three-dimensional NAND flash memory structure 100 may include (extending from the core) a polysilicon channel layer 105, a tunnel oxide layer 110 surrounding the polysilicon layer 105, a charge trapping layer associated with the tunnel oxide layer 110 layer 115 , such as an O / N / O stacked silicon nitride layer, a blocking oxide layer 120 surrounding ...

AI Technical Summary

Problems solved by technology

As can be seen, this early reservation threatens multilevel cell capability and tight V T distribution, and may result in a significant shift 262 of the distribution, such that a verification failure occurs, e.g., at 270

Potentially, read operations after a given time since the programming event could also fail due to this effect if no calibration mechanism is provided

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