Interconnection substrate with elastic conductive micro bumps and KGD socket based on interconnection substrate

Abstract

The invention discloses an interconnection substrate with elastic conductive micro bumps and a KGD socket based on the interconnection substrate, and belongs to the technical field of advanced electronic packaging. According to the invention, a three-dimensional metal electrical interconnection electrical path structure and a coplanar structure between the conductive elastic micro bumps and firstelastic micro bumps are constructed in the interconnection substrate with the elastic conductive micro bumps, so that in the KGD socket based on the interconnection substrate, high-precision positioning placement of a tested chip in the KGD socket can be realized by adopting a chip inversion technology in a matched manner; efficient and high-density electrical interconnection between chip bumps orchip bonding pads and the conductive elastic micro bumps on the interconnection substrate with the elastic micro bumps can be achieved; and meanwhile, scratches are prevented from being left on chipbumps in subsequent matched use and stress of chip inversion, relative movement or falling off of the chips is also prevented, and the technical problem that the density, precision, coplanarity and number of spring needle arrays of an existing KGD socket cannot meet the test requirements of ultra-large-scale integrated circuit bare chips is solved.

Description

technical field [0001] The invention belongs to the technical field of advanced electronic packaging, and relates to an interconnect substrate with elastic conductive micro bumps and a KGD socket based on it. Background technique [0002] While the demand for the diversification and complexity of electronic system functions is gradually increasing, the volume, power consumption and weight of electronic systems are required to be further reduced, which promotes the rapid development of electronic integration technology. Hybrid integration of multiple bare chips in various forms has become the most effective and fastest way to meet the needs of modern electronic systems. COB (chip-on-board), SiP (System-in-Package), SoP (System-on-Package), CoWoS (Chip-on-wafer-on-substrate), 2.5D / 3D integration and other concepts and technologies emerge in endlessly . The above integration generally involves multiple bare chips. Even though these bare chips have passed the ATE test, due to ...

AI Technical Summary

Problems solved by technology

The interconnect substrate with elastic conductive micro-bumps and the KGD socket based on the present invention solve the problem that the density, precision and coplanarity of the pogo pin array of the current KGD socket cannot meet the test requirements of VLSI bare chips The problem

Images