Hypergraph division method supporting interconnection constraints

Abstract

The invention discloses a hypergraph division method supporting interconnection constraints. The method comprises the following steps: 1, traversing all nets; 2, finding out all illegal nets from allthe nets; 3, selecting an illegal net needing to be processed currently from all the illegal nets as a first to-be-processed net based on a first preset sequence, and determining a movement scheme ofa node group at one end of the first to-be-processed net according to movement characteristics of nodes in the node group of the first to-be-processed net; and 4, according to the mode in the step 3,traversing all the illegal nets to obtain a final division scheme. According to the method, the constraints of interconnection resources are considered in the division stage, and the division across the wire net is changed through the movement of a plurality of nodes, so that the wire net is moved, and an illegal wire net is eliminated; in the moving process, gain calculation is considered, that is, the increase situation of the cutting cost caused by movement is judged in advance, and the movement with the maximum gain is selected to be executed, so that the increase of the cutting cost is small, and the performance is guaranteed.

Description

technical field [0001] The invention belongs to the technical field of integrated circuits, and in particular relates to a hypergraph division method supporting interconnect constraints. Background technique [0002] FPGA (Field Programmable Gate Array) is a field programmable gate array, which belongs to a semi-custom circuit in an application-specific integrated circuit. Using FPGA for hardware simulation allows designers to design complex VLSI ( VLSI, Very Large Scale Integration) for functional verification. The FPGA hardware structure includes different types of resources, generally including look-up tables (LUT, Look-Up-Table), flip-flops, digital processing units (DSP, Digital Signal Processing), block storage (Block RAM, BRAM), etc. The designed circuit is often large in scale, so that a single FPGA cannot accommodate the entire circuit design, so the circuit needs to be split into multiple parts and put into different FPGAs, and each part needs to meet the resource...

AI Technical Summary

Problems solved by technology

[0006] But for the actual FPGA, there may be no interconnection resources between the two. If there are connections between such paths during division, it is impossible to directly Using TDM, it will be transferred from other FPGAs with interconnect resources during the routing stage, which will increase the cost and reduce performance

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