Force steering layout method for expanding a crowded area based on maximum flow algorithm

Abstract

The invention discloses a force steering layout method for expanding a crowded area based on a maximum flow algorithm, which relates to the technical field of FPGA layouts, and comprises the followingsteps of: in the process of performing analytic expression algorithm iteration by using a force steering layout algorithm model, periodically selecting a target area with high layout crowding degreeto abstractly establish a residual graph and assign the residual graph; solving the residual graph based on a minimum cost and maximum flow algorithm, wherein before the global layout meets an exit condition, the redistributable node obtains a legal iterative position according to the position of the current layout state; adding the virtual stress application point of the reconfigurable node at the iteration position for traction,wherein the reconfigurable node has a trend of moving to a legal iteration position, the expansion speed of a crowded area can be accelerated in a guided manner, theiteration frequency of an analytic expression algorithm is reduced, the running time is shortened, and the layout efficiency is improved.

Description

technical field [0001] The invention relates to the technical field of FPGA layout, in particular to a force-directed layout method for expanding crowded areas based on a maximum flow algorithm. Background technique [0002] Field-Programmable Gate Array (Field-Programmable Gate Array, FPGA) is a chip widely used in household appliances, large machinery and even aerospace. The use of FPGA chips is inseparable from electronic design automation (Electronic Design Automation, EDA) tools. Layout is an important part of the EDA tool, which has a great impact on the running speed of the EDA tool itself and the final quality of the processed circuit. In recent years, the circuit scale of FPGA chips has grown rapidly, making its functions more powerful, but it has also brought challenges to the corresponding EDA tools. [0003] The main function of the layout is to map the functional modules in the input netlist to the layout position of the FPGA chip with actual physical coordina...

AI Technical Summary

Problems solved by technology

However, the solution results of the analytical layout algorithm often have the problem of overlapping functional modules, and the prerequisite for a legal layout is that there is no overlap between the functional modules. Generally, there will be a large number of layout results obtained by the analytical layout algorithm in the first few solutions. Overlap, multiple iterations are required to expand the solution results until reaching an ideal low overlap degree, but even the last iteration often cannot completely eliminate the overlap of the layout results, so the analytical layout algorithm usually still needs to be combined with legalization processing In order to obtain a reasonable layout result

The circuit structure of the current input netlist is often bulky, and often requires multiple iterations to expand the overcrowded area, so the processing time of the iterative expansion process is usually longer, reducing layout efficiency

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