Design method of QFN chip heat dissipation bonding pad steel mesh

Abstract

The invention discloses a QFN chip heat dissipation pad steel mesh design method comprising the following steps: S1, obtaining QFN chip pad information comprising the chip pad size, the chip pad spacing and the chip pad solder resist information; S2, setting the shape, the array mode and the spacing of the steel mesh according to the QFN chip bonding pad information; and S3, creating an array typesteel mesh on the QFN chip bonding pad. The QFN chip steel mesh is designed in an array block mode, a channel covered with solder resist oil is reserved in the middle of the QFN chip steel mesh, gasgenerated by scaling powder can be exhausted from the channel in the welding process, and the problem of poor welding caused by blocking of gas exhaust is solved. Because the welding points of the QFNchip heat dissipation bonding pads are arranged at the bottom of the device, the array type steel mesh design can effectively avoid bridging and open circuit with peripheral devices; the service lifeof the QFN chip can be prolonged while the electrical performance is satisfied, and the production cost is saved.

Description

technical field [0001] The invention relates to the technical field of QFN packaging, in particular to a design method of a QFN chip cooling pad steel mesh. Background technique [0002] With the rapid development of electronic technology, electronic components are becoming more and more miniaturized and integrated, which will lead to the continuous increase of the internal current density of the components. According to the analysis of the reliability data of electronic components, most of the failures of electronic components are due to the internal heat conduction of the components. Poor cycle, caused by temperature rise of components; our current commonly used four-sided leadless flat package has good electrothermal performance, small size and light weight and is widely used in various chip packaging technologies. [0003] However, QFN is a leadless package with a square or rectangular shape. There is a large-area exposed pad at the center of the bottom of the package fo...

AI Technical Summary

Problems solved by technology

At present, in the design process of QFN chip component packaging, most of the stencils are designed to be the same copper skin as the pad. When the QFN chip and PCB are soldered, the two are very close. The plate is large, and when the solder paste and flux are heated, a large amount of gas will be generated. Because the heat dissipation pad is surrounded by solder feet, some of the gas cannot be discharged, and air bubbles will form between the chip and the PCB package, resulting in poor soldering.

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