A six-layer wiring LCP package substrate, manufacturing method and multi-chip system-in-package structure

A technology for packaging substrates and substrates, which is applied in semiconductor/solid-state device manufacturing, semiconductor/solid-state device components, semiconductor devices, etc., to achieve high assembly efficiency, low moisture absorption and water permeability, oxygen transmission rate, and excellent high-frequency transmission characteristics Effect

Active Publication Date: 2022-04-12
SOUTHWEST CHINA RES INST OF ELECTRONICS EQUIP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0016] The existing disclosed technology has not yet used LCP to realize the technical solution of packaging substrate and system-in-package structure that meets the system-in-package requirements of multi-chip, high airtightness requirements, high electromagnetic shielding, and highly reliable interconnection.

Method used

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  • A six-layer wiring LCP package substrate, manufacturing method and multi-chip system-in-package structure
  • A six-layer wiring LCP package substrate, manufacturing method and multi-chip system-in-package structure
  • A six-layer wiring LCP package substrate, manufacturing method and multi-chip system-in-package structure

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0078] Such as figure 1 As shown, a six-layer wiring LCP packaging substrate of this embodiment includes:

[0079] 6 layers of patterned metal circuit layers distributed from the surface to the bottom surface, followed by the first layer of patterned metal circuit layer, the second layer of patterned metal circuit layer, the third layer of patterned metal circuit layer, and the fourth layer of patterned metal circuit layer layer, the fifth layer of patterned metal circuit layer, and the sixth layer of patterned metal circuit layer; on at least one side of the outermost edge of the first layer of patterned metal circuit layer, the external secondary cascading of the LCP packaging substrate is distributed Pads or graphics for I / O soldering;

[0080] 5 layers of insulating dielectric layers located between adjacent patterned metal circuit layers; each layer of the insulating dielectric layer is composed of an LCP substrate;

[0081] Located in the insulating dielectric layer be...

Embodiment 2

[0098] Such as image 3 As shown, this embodiment provides a method for manufacturing the six-layer wiring LCP packaging substrate 1 as described in Embodiment 1, including the following steps:

[0099] S1, such as Figure 4a As shown, blind holes are laser drilled on the double-sided copper-clad LCP substrate 153 to form third-type blind holes 143 that penetrate and connect the third patterned metal circuit layer 113 and the fourth layer patterned metal circuit layer 114. The blind holes Depth-to-diameter ratio≤1;

[0100] S2, such as Figure 4b As shown, the metallization of blind holes forms the third type of blind holes 143 filled with solid electroplated copper; The electroplating copper process is realized. After hole filling electroplating, the copper plating layer on the surface is thinned to form a third type of blind hole 143 filled with solid electroplated copper;

[0101] S3, such as Figure 4c As shown, the third layer of patterned metal circuit layer 113 and...

Embodiment 3

[0112] Such as Figure 5 As shown, based on the LCP packaging substrate described in Embodiment 1-2, this embodiment provides a multi-chip system-in-package structure 2, including: the LCP packaging substrate 1 as described in Embodiment 1-2, and chips 3, Metal enclosure 5 and metal cover plate 6;

[0113] The multi-chip system-in-package structure 2 is fixed on the PCB mother board by means of conductive adhesive bonding or welding, and the pads or patterns 1111 for external secondary cascading I / O welding on the LCP packaging substrate 1 are used. As the external secondary cascade I / O interface of the multi-chip system-in-package structure 2;

[0114] Metal ribs 51 are distributed in the metal surrounding frame 5; the metal surrounding frame 5 and the metal ribs 51 are welded on the upper surface of the LCP package substrate 1 and make the external secondary cascaded I / O welding pads or The figure 1111 is outside the metal frame 5, and the metal cover plate 6 is welded on ...

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Abstract

The invention discloses a six-layer wiring LCP packaging substrate, a manufacturing method and a multi-chip system-level packaging structure. The LCP packaging substrate comprises: six layers of patterned metal circuit layers distributed from the surface to the bottom, and a first layer of patterned metal circuit layers. At least one edge of the outermost periphery of the circuit layer is distributed with pads or patterns for external secondary cascade I / O soldering of the LCP package substrate; 5 layers of insulating dielectric layers located between adjacent patterned metal circuit layers; in the insulating dielectric layer between the first patterned metal circuit layer and the second patterned metal circuit layer, and the openings face a plurality of blind grooves of the first patterned metal circuit layer; located in the patterned metal circuit layer Multiple blind holes between the insulating dielectric layer. The invention realizes an LCP package substrate with a hermetic packaging structure that can meet the system-level packaging requirements of multi-chips, high air tightness requirements, high electromagnetic shielding and high reliability interconnection.

Description

technical field [0001] The invention relates to the technical field of integrated circuits and chip packaging, in particular to a six-layer wiring LCP packaging substrate, a manufacturing method and a multi-chip system-level packaging structure, which are used for high-reliability system-level applications for high-frequency applications such as radio frequency, microwave, and millimeter wave. encapsulation. Background technique [0002] With the advancement of semiconductor and integrated circuit technology, the requirements for system integration have been further improved. The current design and manufacture of electronic circuits are moving towards smaller sizes and higher integration densities. Considerable work is carried out in the field of multi-chip packaging. In the advanced packaging form, multiple radio frequency (RF) chips, digital integrated circuit (IC) chips, micro-chip components, etc. are assembled on the packaging substrate through SIP technology, and then ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L23/538H01L23/498H01L23/552H05K1/09H01L21/48H01L21/768
CPCH01L23/49894H01L23/49838H01L23/5386H01L23/552H01L23/49816H05K1/09H01L21/4846H01L21/4853H01L21/76895H01L2224/48091H01L2924/00014
Inventor 徐诺心戴广乾龚小林林玉敏边方胜潘玉华蒋瑶珮谢国平匡波向伟玮
Owner SOUTHWEST CHINA RES INST OF ELECTRONICS EQUIP
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