Stacked bonding type IGBT device
A technology of device and MOS structure, which is applied in the direction of electric solid-state devices, semiconductor devices, semiconductor/solid-state device components, etc., to achieve the effect of reducing manufacturing costs
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Embodiment 1
[0038] Take an N-type Si wafer, and make a power MOS structure on it, and the terminal part of the MOS structure has a withstand voltage of 900V. After all the front structures are fabricated, the Si wafer is thinned from the back to a thickness of 95um. Carry out dicing and cutting to obtain MOS structure "chiplets" one by one. The gate electrode and cathode of the future IGBT device are the gate electrode and source of the MOS structure, which have been fabricated on the upper surface of each "small chip" and drawn out from there.
[0039] Another piece of P+ type Si wafer was taken, and the multi-layer epitaxy technology was used to epitaxially grow N-layer 5um, N+ layer 1um, and N-layer 14um on the wafer sequentially, with a total epitaxial layer thickness of 20um. For the epitaxial wafer, a terminal structure is fabricated on its upper surface, and the terminal structure withstands a voltage of about 150V. For this substrate sheet, the bottom surface is metallized to ma...
Embodiment 2
[0044] For the MOS structure and PN junction structure, the metallized contact surface is additionally prepared, that is, after the MOS structure is processed and the wafer is thinned from the back, the back metallization step is added to obtain a 0.5um metal Al thin layer, and then On the upper surface of the wafer with a PN junction structure, a metallization step is added to the area inside the guard ring to obtain a 0.5um metal Al thin layer.
[0045] The remaining device structures and implementation methods are the same as those in Embodiment 1.
[0046] This embodiment is a change to the basic embodiment 1. Due to the additional process steps, the metal Al contact surfaces are prepared for both the upper and lower structures, so the contact between the two can be achieved through the "metal-to-metal" Bonding is strengthened. In addition, it should be pointed out that the metallization of semiconductor materials here is very mature in technology, does not require specia...
Embodiment 3
[0048] The rest of the steps are the same as in Embodiment 1, but two kinds of substrates are prepared. One of them is the same as Embodiment 1, and the other adopts the following parameters: the multilayer epitaxy is N-layer 5um, N+ layer 1um, N-layer 34um, and the total epitaxial layer thickness is 40um. For the epitaxial wafer, a terminal structure is fabricated on its upper surface, and the terminal structure withstands a voltage of about 350V.
[0049] The same upper MOS structure is combined with different substrates respectively to obtain IGBT devices of two specifications with a withstand voltage of 1000V and a withstand voltage of 1200V.
[0050] Embodiment 3 provides a very flexible function, that is, the part of the MOS structure with higher manufacturing cost can be manufactured according to one specification, and the part of the PN junction structure with lower manufacturing cost can be flexibly changed to obtain different specifications ( The additional cost is ...
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