Compact arithmetic accelerator for data processing devices, systems and methods
An accelerator and data technology, applied in the direction of electrical digital data processing, special data processing applications, digital data processing components, etc., can solve problems affecting system battery life, cost and efficiency, etc.
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example A2
[0147] Example A2 includes the method of example A1 , wherein writing the vector data into the internal memory, computing the vector operation, and writing the output into the system memory is implemented in a pipelined scheme.
[0148] Example A3 includes the method of example A2, wherein the pipelining scheme for processing the vector operation by the accelerator device utilizes fewer clocks than if the vector operation is processed by the data processing unit cycle.
[0149] Example A4 includes the method of example A2, wherein the pipelining of writing the vector data into the internal memory, computing the vector operation, and writing the output into the system memory is performed simultaneously of.
[0150] Example A5 includes the method of Example A1 , wherein the vector operations include one or more of: (i) a signal processing function that includes a Fast Fourier Transform (FFT) and a Finite Impulse Response (FIR ) one or both of the filters; (ii) a linear algebra...
example A6
[0151] Example A6 includes the method of example A1, further comprising, prior to computing, receiving a run command at the accelerator to perform the vector operation.
[0152] Example A7 includes the method of example A1, wherein the command received includes two or more vector operations, and wherein computing each of the two or more vector operations is computed in serial.
[0153] In some embodiments (Example A8) in accordance with the present technology, a data processing accelerator for processing vector operations includes a configuration register for receiving and storing data for a vector from a data processing unit of an electronic system Operation commands and associated information, the associated information includes the read address in the system memory where the vector data is located, the data length of the vector data, and the address in the system memory used to write the output of the vector operation a write address; an address generator configured to gene...
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