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Multi-chip packaging device

A multi-chip packaging and device technology, which is applied in the fields of electric solid-state devices, semiconductor devices, semiconductor/solid-state device components, etc., can solve problems such as alignment, and achieve the effects of improving yield, reducing device cost, and reducing alignment difficulty.

Pending Publication Date: 2021-03-12
NANTONG FUJITSU MICROELECTRONICS
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  • Abstract
  • Description
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Problems solved by technology

[0004] This application provides a multi-chip packaging device to solve the alignment problem in the preparation process of the multi-chip packaging device

Method used

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Embodiment Construction

[0026] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, but not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the protection scope of the present application.

[0027] see figure 1 , figure 1 It is a schematic structural diagram of an embodiment of a multi-chip packaged device of the present application. The multi-chip packaged device includes a first wafer 10 , a plurality of electrical connectors 101 and a plurality of bridge chips 103 .

[0028] Specifically, as figure 2 shown, figure 2 for figure 1 A schematic top view of an embodiment of the first wafer in FIG. The first wafer 10 is provided ...

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Abstract

The invention provides a multi-chip packaging device which comprises a first wafer, the first wafer being provided with a plurality of main chips arranged in a matrix mode, a first scribing groove being formed between every two adjacent main chips, the first wafer comprising a front face and a back face which are arranged oppositely, the front faces of the main chips being the front faces of the first wafer, the back surface of the main chip being the back surface of the first wafer, and the front surface of the main chip being provided with a plurality of first bonding pads; a plurality of electric connecting pieces, wherein one electric connecting piece is arranged at the position of one first bonding pad; a plurality of bridging chips, one bridging chip being arranged above the two adjacent main chips in a bridging manner, and being electrically connected with the electric connecting piece at the corresponding position, so that the two adjacent main chips are electrically connectedthrough one bridging chip. Through the design mode, the alignment problem in the preparation process of the multi-chip packaging device can be solved.

Description

technical field [0001] The present application belongs to the technical field of packaging, and in particular relates to a multi-chip packaging device. Background technique [0002] With the upgrading of electronic products, there are more and more functional requirements for multi-chip packaged devices, and signal transmission between multiple chips in the multi-chip packaged device is also more and more frequent. Currently, a silicon bridge or the like is generally used to form an electrical interconnection structure between multiple chips to realize signal transmission. [0003] The existing process of forming the above-mentioned multi-chip package device mainly includes: firstly cutting a single chip from a wafer, then redistributing the multiple chips on the substrate, and then realizing the silicon bridge and the multiple chips at the corresponding positions. electrical connection. The above-mentioned redistribution process requires higher alignment accuracy and high...

Claims

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Application Information

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IPC IPC(8): H01L23/52H01L23/48H01L23/488
CPCH01L23/52H01L23/481H01L23/488
Inventor 李骏戴颖黄金鑫
Owner NANTONG FUJITSU MICROELECTRONICS
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