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RISC-V universal processor supporting high-throughput multi-precision multiplication operation

A RISC-V, general-purpose processor technology, applied in the direction of electrical digital data processing, digital data processing components, instruments, etc., can solve problems such as low-precision bit width, low-precision processors, and inability to handle multi-precision calculations. To achieve the effect of doubling the bandwidth

Active Publication Date: 2021-03-16
SHANGHAI JIAO TONG UNIV
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  • Abstract
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  • Application Information

AI Technical Summary

Problems solved by technology

General-purpose processors still insist on using 32-bit or 64-bit word width in the design of computing circuits. The main reasons are: 1) The operands in general-purpose workloads usually have different word widths. Cannot reduce the bit width of the internal operation unit to a low-precision bit width as fast as the neural network accelerator
2) In order to ensure backward compatibility, that is, the latest general-purpose processors can run old program codes, it is difficult to quickly change general-purpose processors to low-precision processors
Among all the arithmetic circuits in general-purpose processors, multipliers occupy the core position, so the current general-purpose processors have the defect of being unable to handle multi-precision calculations

Method used

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  • RISC-V universal processor supporting high-throughput multi-precision multiplication operation
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  • RISC-V universal processor supporting high-throughput multi-precision multiplication operation

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Embodiment Construction

[0018] The present invention will be described in detail below with reference to the specific embodiments. The following examples will help to further understand the present invention in any form of technicrat, it will be further understood by those skilled in the art. It should be noted that several variations and improvements can be made without departing from the concept of the present invention without departing from the present invention. These are all of the scope of protection of the present invention.

[0019] A RISC-V universal processor that supports high-throughput multi-precision multiplication operations, such as figure 1 As shown, a general-purpose RISC-V processor micro-architecture design based on high throughput multi-precision multipliers is proposed, and the basic five-level pipeline design is made, and the finger, decoding, execution, interview, and backwritten. The specific microarching innovation point is as follows:

[0020] 1, independent multiplier data p...

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Abstract

The invention provides an RISC-V universal processor supporting high-throughput multi-precision multiplication, which comprises an independent multiplier data path; the multiplier data path separatesa data path of a multi-precision multiplier from data paths of other operation units; and the multi-precision instruction directly enters a register write-back stage without passing through a memory access stage after an execution stage, so that the use of a pipeline register is reduced, the area and the power consumption are saved, and the multi-precision multiplier is provided with an independent data path for writing a floating point multiplication result into a vectorized register file VRF. The RISCV general processor supporting high-throughput multi-precision multiplication operation provided by the invention can efficiently process multi-precision calculation requirements.

Description

Technical field [0001] The present invention relates to the technical field of universal processors, and in particular, to a RISC-V universal processor that supports high-throughput multi-precision multiplication. Background technique [0002] Since Intel 80386, 32-bit or 64-bit words have become a conventional method in a general purpose processor, which is considered a conventional method in today's arithmetic logic unit (ALU), architecture, and algorithm. The popularity of deep neural networks makes the accelerated neural network a new design direction, which can be reduced by smaller weight data for the neural network to obtain smaller weight data, which can reduce the cost of the force and the overhead of memory bandwidth. For example, Google's TPU supports the low precision format of the floating point format; NVIDIA adds TENSorcore cores facing more accuracy in its latest GPU to accelerate universal matrix multiplication. [0003] So far, universal processors have not adde...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F7/523G06F7/487G06F9/30
CPCG06F7/523G06F7/4876G06F9/3001G06F9/30181G06F9/30098Y02D10/00
Inventor 景乃锋王琴张茂全徐磊蒋剑飞
Owner SHANGHAI JIAO TONG UNIV
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