Semiconductor structure manufacturing method

Abstract

The invention relates to a semiconductor structuremanufacturing method, which comprises the following steps of: providing a substrate which is provided with a plurality of discrete conducting layers;forming a precursor layer covering the top and the side wall of the conductive layer on the substrate; pre-oxidizing the precursor layer to convert the precursor layer higher than the top of the conductive layer into a first barrier layer; and then, annealing the precursor layer located below the first barrier layer in an oxygen-containing atmosphere, and generating gas in the precursor layer to form an isolation layer with a plurality of air holes. According to the embodiment of the invention, the first barrier layer is formed, in the annealing treatment process, the oxygen-containing gas permeates into the precursor layer through the first barrier layer, and the first barrier layer can prevent gas generated by oxidation of the precursor layer from being discharged, so that the precursorlayer is converted into the porous isolation layer with higher pore density and larger pore volume; and the dielectric constant of the isolation layer material is reduced, so that the interconnectiondelay effect of the semiconductor structure is reduced, and the signal transmission speed is increased.

Description

Technical field [0001] The present invention relates to the field of semiconductor technology, and more particularly to a semiconductor structure manufacturing method. Background technique [0002] Currently, in the field of semiconductor technology, the semiconductor is moving towards super sub-microns, and the size of the semiconductor structure has become less and smaller. As the semiconductor structure size is reduced, the cross section and line spacing of the interconnect leads are also reduced, which makes the interconnect delay effect be more severe, and correspondingly, the operating speed of the semiconductor structure is slowed down. [0003] In order to solve the interconnect delay effect, a low-k dielectric material is usually employed as a material of the isolation layer between the adjacent conductive layers. At present, a porous isolation layer is typically provided between adjacent conductive layers, which has a pore such that the relative dielectric constant of t...

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Problems solved by technology

[0004] However, in the existing process flow, the number of pores in the formed porous isolation layer is too small and the volume is too small, resulting in a high dielectric constant of the porous isolation layer, which cannot adapt to the current development of smaller and smaller semiconductor structures. trend

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