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Efficient FPGA integrated verification method

A verification method and efficient technology, applied in the field of FPGA, can solve the problems of low efficiency, long verification time, and time-consuming integration verification, and achieve the effects of improving simulation efficiency, shortening configuration time, and shortening simulation time.

Active Publication Date: 2021-04-02
WUXI ESIONTECH CO LTD +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The more logic resources contained in the verification object, the larger the number of test cases, the longer the verification time will be consumed, resulting in the integration verification of existing FPGA chips is often time-consuming and inefficient

Method used

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  • Efficient FPGA integrated verification method
  • Efficient FPGA integrated verification method
  • Efficient FPGA integrated verification method

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Embodiment Construction

[0026] The specific embodiments of the present invention will be further described below in conjunction with the accompanying drawings.

[0027] This application discloses an efficient FPGA integrated verification method, please refer to figure 1 Shown in the flow chart, the method comprises the steps:

[0028] Step S1, use software to generate a corresponding fully configured code stream according to the function of the target test case. The fully configured code stream is used to configure the entire FPGA chip. The entire FPGA chip includes a large number of logic resources, such as figure 2 As shown, the logic resources in the FPGA chip mainly include various basic logic units 1 and interconnection resources 2, and these logic resources are arranged according to a predetermined structure.

[0029] Step S2, analyzing the full configuration code stream, dividing the full configuration code stream into several frames in units of frames, and obtaining the frame header field, ...

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Abstract

The invention discloses an efficient FPGA integrated verification method, which relates to the technical field of FPGAs, and comprises the following steps of after analyzing a full-configuration codestream to obtain a frame header field, a configuration register field and a frame tail field, cutting the configuration register frame field according to a logic resource area occupied by a target test case, and generating the reduced configuration code stream together with the frame header field and the frame tail field. As the configuration code stream is reduced, so that the time for downloading and configuring the code stream data can be greatly reduced, the simulation time can be effectively shortened, the simulation efficiency is improved, and the configuration time for FPGA full-chip integration verification is greatly shortened.

Description

technical field [0001] The invention relates to the field of FPGA technology, in particular to an efficient FPGA integration verification method. Background technique [0002] As FPGA chips become more integrated and their functions more powerful, the complexity and importance of FPGA chip verification are also increasing. In the verification process of the entire FPGA chip, in addition to the verification of basic functional modules (also called basic logic units), the key points and difficulties of the entire verification process are concentrated on verifying the correctness of the connection relationship between a large number of basic logic units. , The correctness verification of the connection relationship between the basic logic units also becomes the integration verification of the FPGA chip. [0003] Integrated verification of FPGA chips targets all chip circuits of different scales and different areas of all chips. For different verification objects, integrated ve...

Claims

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Application Information

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IPC IPC(8): G06F30/33
CPCG06F30/33
Inventor 娄秀丽丛红艳闫华张艳飞赵赛
Owner WUXI ESIONTECH CO LTD