3D memory device and manufacturing method thereof

Abstract

The invention discloses a 3D memory device and a manufacturing method thereof. The 3D memory device comprises a CMOS circuit and amemory unit array. The memory unit array comprises a laminated structure which comprises a plurality of interlayer dielectric layers and a plurality of gate conductors alternately stacked, a plurality of channel columns penetrating through the laminated structure, a common source region which is electrically connected with one end of each channel column and a conductive plug. The other end of each channel column is electrically connected with the CMOS circuit; and the conductive plug is electrically connected with the common source region and extends from the common source region to the surface, far away from the CMOS circuit, of the memory cell array, so that a shorter conductive path is provided, and the conductive plug can also be used as a discharge path in the manufacturing process of the 3D memory device so as to protect the 3D memory device.

Description

technical field [0001] The invention relates to the technical field of memory, in particular to a 3D memory device and a manufacturing method thereof. Background technique [0002] The improvement of the storage density of the memory device is closely related to the progress of the semiconductor manufacturing process. As the feature size of the semiconductor manufacturing process becomes smaller and smaller, the storage density of the memory device becomes higher and higher. In order to further increase storage density, memory devices with a three-dimensional structure (ie, 3D memory devices) have been developed. A 3D memory device includes a plurality of memory cells stacked in a vertical direction, which can double the integration level on a wafer per unit area and reduce the cost. [0003] Existing 3D memory devices are mainly used as non-volatile flash memory. The two main non-volatile flash memory technologies use NAND and NOR structures, respectively. Compared with...

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Problems solved by technology

In this 3D memory device, a large number of metal wirings are used to provide the electrical connection between the CMOS circuit and the memory cell array, and the increase in wiring density will affect the yield and reliability of the 3D memory device.

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