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Chip packaging structure and packaging method thereof

A chip packaging structure and chip technology, applied in electrical components, electrical solid devices, circuits, etc., can solve problems such as poor integration of chip packaging structures, and achieve the effect of improving integration.

Active Publication Date: 2021-04-09
SHANGHAI XIANFANG SEMICON CO LTD +1
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] Therefore, the technical problem to be solved by the present invention is to overcome the problem of poor integration of chip packaging structure in the prior art

Method used

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  • Chip packaging structure and packaging method thereof
  • Chip packaging structure and packaging method thereof
  • Chip packaging structure and packaging method thereof

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Embodiment Construction

[0029] After research, it is found that when packaging the memory chip and the control chip, one solution is: put the storage chip and the control chip on the same side of the package carrier; the other solution is: set the memory chip on one side of the package The other side of the carrier is provided with a control chip. Both of these two solutions use plastic packaging materials to completely wrap the memory chip and the control chip. Since the packaging carrier is a PCB board, the process node and size of the packaging carrier are relatively large. Since both the memory chip and the control chip protrude from the surface of the packaging carrier, the volume of the package is larger, which is not conducive to higher density packaging requirements.

[0030] Furthermore, due to the use of a large amount of plastic packaging materials, it is not conducive to the heat dissipation of the packaging carrier, but also causes a large warpage, which affects the reliability of the s...

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Abstract

The invention discloses a chip packaging structure and a packaging method thereof, and the chip packaging structure comprises: a carrier substrate, which is provided with a first surface, and is internally provided with a chip accommodation groove facing the first surface; a plurality of built-in chips, which are positioned in the chip accommodating groove and are arranged in a stacked manner along the direction perpendicular to the bottom surface of the chip accommodating groove; and a rewiring structure, which is located on the first surface, covers the plurality of built-in chips, and is electrically connected with the built-in chips. The integration level of the chip packaging structure is improved.

Description

technical field [0001] The invention relates to the packaging field, in particular to a chip packaging structure and a packaging method thereof. Background technique [0002] With the continuous development of integrated circuit technology, electronic products are increasingly developing in the direction of miniaturization, intelligence, high performance and high reliability. The integrated circuit packaging not only directly affects the performance of integrated circuits, electronic modules and even the whole machine, but also restricts the miniaturization, low cost and reliability of the entire electronic system. With the gradual reduction of the size of the integrated circuit chip and the continuous improvement of the integration level, the electronic industry has put forward higher and higher requirements for the integrated circuit packaging technology. Therefore, how to improve the integration degree of the packaging structure is an important subject in this field. C...

Claims

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Application Information

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IPC IPC(8): H01L25/16H01L23/31H01L21/56H01L23/488H01L21/60
CPCH01L25/162H01L23/3128H01L24/02H01L24/13H01L24/11H01L21/56H01L2224/02381H01L2224/02372H01L2224/13008H01L2224/111
Inventor 张凯曹立强耿菲
Owner SHANGHAI XIANFANG SEMICON CO LTD
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