Novel time sequence pipeline ADC based on inter-stage buffer isolation

Abstract

The invention discloses a novel time sequence pipeline ADC based on inter-stage buffer isolation. The novel time sequence pipeline ADC comprises a new time sequence generation circuit used for generating a preceding-stage clock and a backward-stage clock of the pipeline ADC, wherein the time ratio of a sampling phase in the preceding-stage clock and the backward-stage clock to phase distribution established by residual amplification is 1:a; an assembly line preceding-stage circuit used for sampling and amplifying an input signal according to a preceding-stage clock to obtain a residual signal; a buffer isolation circuit used for carrying out isolation processing on the residual signal to obtain a residual isolation signal; and an assembly line post-stage circuit used for sampling and amplifying the residual isolation signal according to a post-stage clock to obtain an output signal. According to the invention, a novel working time sequence is adopted, and more time is allocated for residual error amplification establishment, so that the working speed of a front-stage circuit and a rear-stage circuit of an assembly line is improved, and the conversion rate of the ADC of the whole assembly line is further improved.

Description

technical field [0001] The invention belongs to the technical field of mixed-signal integrated circuit circuits, and in particular relates to a novel timing pipeline ADC based on inter-stage buffer isolation. Background technique [0002] The pipeline structure analog-to-digital converter (Analog-to-digital Converter, referred to as ADC) is a common structure for realizing high-speed and high-precision ADC, which has a good balance in terms of accuracy, speed, and power consumption. The speed is fast, so it is more and more widely used in high-speed and high-precision fields such as wireless communication and digital video. [0003] The improvement of the pipeline ADC sampling rate is mainly limited by the settling time of the residual amplification. In the case of the same amplifier speed in the pipelined ADC, the allocation of more residual amplification settling time means that the pipelined ADC can achieve higher conversion rates. For traditional pipelined ADCs, since t...

AI Technical Summary

Problems solved by technology

[0004] However, the pipeline ADC allocated according to the 1:1 timing relationship, due to the limitation of the establishment speed of the amplifying circuit, the conversion rate of the pipeline ADC is limited

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