Half-bridge semiconductor device

Abstract

This disclosure relates to a discrete half bridge semiconductor device comprising: a first cascode arrangement and a second cascode arrangement; each of the first cascode and second cascode arrangements comprising a high voltage FET device die and a low voltage FET device die; wherein the source of the high voltage FET device die is mounted on and connected to a drain of the low voltage FET device die; and the source of the low voltage FET device die and gate of the high voltage FET device die are connected to a drain terminal of the high voltage FET device die of the second cascode arrangement at common connection pad.

Description

technical field [0001] The present disclosure relates to discrete half-bridge semiconductor devices. In particular, the present disclosure relates to a discrete half-bridge semiconductor device comprising a cascode arrangement of depletion-mode transistor dies and enhancement-mode transistor dies, and an associated method of assembling such a discrete half-bridge semiconductor device . Background technique [0002] Cascode arrangements of transistors are well known, especially for controlling a zero gate-source voltage, high voltage semiconductor die normally on (or depletion mode) using a normally off, low voltage semiconductor die. Cascode arrangements can be used in switched mode applications, especially in power supplies where efficient energy switching is required. [0003] Typically, an external connection between the two cascode arrangements 100, 100' is implemented such as figure 1 A half-bridge arrangement of the type shown in . External connections may be arran...

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Problems solved by technology

[0007] Furthermore, the above-mentioned known arrangements are complex to manufacture and require two separate and optimized device packages to form the above-mentioned half-bridge arrangement

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