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Semiconductor device and erasing and verifying method for semiconductor device

A verification method, semiconductor technology, applied in instruments, static memory, read-only memory, etc., can solve problems such as unfavorable erasure verification accuracy

Active Publication Date: 2021-04-20
YANGTZE MEMORY TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, when erasing memory cells in a NAND string, there is a risk of HCI (Hot Carrier Injection), which is not conducive to improving the accuracy of erase verification

Method used

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  • Semiconductor device and erasing and verifying method for semiconductor device
  • Semiconductor device and erasing and verifying method for semiconductor device
  • Semiconductor device and erasing and verifying method for semiconductor device

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Embodiment 1

[0063] Embodiments of the present application provide an erasing and verifying method for a semiconductor device.

[0064] Specifically, combine Figure 1 to Figure 3 As shown, semiconductor device 20 is a three-dimensional memory device, such as 3D NAND memory device 10 . The semiconductor device 20 includes a plurality of memory blocks BLOCK, and selected ones of the plurality of memory blocks include a plurality of memory cell strings 21, eg, a plurality of NAND strings. like image 3 As shown, each memory cell string 21 includes a top select transistor Q1, a bottom select transistor Q2, a plurality of memory cells MC and at least one dummy memory cell DMC arranged in series. In this embodiment, the number of virtual storage units DMC is multiple, but not limited to this. Among them, a plurality of memory cells MC and a plurality of dummy memory cells DMC are located between the top selection transistor Q1 and the bottom selection transistor Q2. The plurality of dummy m...

Embodiment 2

[0090]The embodiment of the present application also provides an erasing and verification method for a semiconductor device, which is different from the above-mentioned embodiment in step S402. This embodiment can solve the negative impact of incomplete erasing on the verification process of selected memory cell strings.

[0091] In this embodiment, in the verification operation phase, the verification operation phase is divided into a pre-conduction phase and a verification phase in turn; in the pre-conduction phase, a selected memory cell string in the plurality of memory cell strings is set as a channel On state; during the verification phase, the threshold voltages of selected memory cells in the selected memory cell strings are verified; and throughout the verification operation phase, the unselected memory cell strings are set to the channel-off state.

[0092] Specifically, combine image 3 , Figure 7 and Figure 8 As shown, in the whole verification operation stage...

Embodiment 3

[0098] The embodiment of the present application also provides an erasing and verification method for a semiconductor device, which is different from the above-mentioned embodiment in step S402. This embodiment can solve the influence of the strong electric field generated by the first turn-on voltage Vpass1 on the dummy word line of the dummy memory cell DMC on the unselected memory cell string.

[0099] In this embodiment, in the verification operation stage, the verification operation stage is divided into a pre-conduction stage and a verification stage in turn; in the pre-conduction stage, unselected memory cell strings in the plurality of memory cell strings are set as channel In the verification stage, the unselected memory cell strings are set to the channel off state, and the selected memory cell strings are set to the channel off state. The threshold voltages of selected memory cells in the memory cell string are verified.

[0100] Specifically, combine image 3 , ...

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Abstract

The invention discloses a semiconductor device and an erasing and verifying method for the semiconductor device. The semiconductor device includes a plurality of memory blocks, a selected memory block of the plurality of memory blocks includes a plurality of memory cell strings, and each memory cell string includes a plurality of memory cells; the erasing and verifying method comprises the following steps: in an erasing operation stage, erasing a plurality of memory cells in each memory cell string; in a verifying operation stage comprising a pre-conduction stage and a verification stage, the plurality of storage unit strings comprising a selected storage unit string and an unselected storage unit string; in the pre-conduction stage, setting at least one of the selected memory cell string and the unselected memory cell string to be in a channel conduction state; in the verifying stage, verifying the threshold voltage of at least one memory cell in the selected memory cell string, and setting the non-selected memory cell string to be in a channel cut-off state. According to the invention, the risk of hot carrier injection can be avoided, and the accuracy of erasure verification of the semiconductor device can be improved.

Description

technical field [0001] The present application relates to a semiconductor device and an erasing and verification method thereof, in particular to a semiconductor device that can avoid the risk of hot carrier injection and an erasing and verification method for the semiconductor device. Background technique [0002] Semiconductor memories are widely used in various electronic devices, such as cellular phones, digital cameras, personal digital assistants, medical electronic devices, mobile computing devices, and non-mobile computing devices. Non-volatile memory allows information to be stored and preserved. Examples of non-volatile memory include flash memory (eg, NAND-type and NOR-type flash memory) and electrically erasable programmable read-only memory (electrically erasable programmable read-only memory, EEPROM). [0003] Recently, ultra-high density memory devices using three-dimensional (3D) stacked memory structures, sometimes referred to as bit cost scalable (BiCS) ar...

Claims

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Application Information

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IPC IPC(8): G11C16/34G11C16/04G11C16/14
CPCG11C16/3445G11C16/14G11C16/0483
Inventor 贾建权李达游开开李楷威罗哲田瑶瑶刘畅李姗张安靳磊
Owner YANGTZE MEMORY TECH CO LTD
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