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Memory bus interface and method used in IC

An integrated circuit, memory technology, applied in the direction of bus network, forward error control use, electrical components, etc., can solve problems such as data packet errors

Inactive Publication Date: 2003-11-05
DEUTSCHE THOMSON-BRANDT GMBH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Sometimes it may appear that part of the data packet is wrong, while another part is available

Method used

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  • Memory bus interface and method used in IC
  • Memory bus interface and method used in IC
  • Memory bus interface and method used in IC

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Embodiment Construction

[0046] exist figure 1 Among them, the physical layer integrated circuit (IC) PLI is connected with the IEEE1394 bus cable B. The PLI on the other side is connected to the integrated circuit (IC) LLI of the link layer for data input and / or data output. Connect the LLI with the application device APP. The microcontroller μP controls the LLI and through the LLI controls the PLI. The application device APP can also be controlled by μP. In other words, the PLI and / or APP can be controlled by a separate microcontroller. μP can complete the above-mentioned CRC check.

[0047] The present invention can be used as figure 2 Application shown: A set-top box STB with receiving unit RU, MPEG decoder MDEC and IEEE1394 interface 1394S receives digital television (TV) programs via satellite or cable. The output signal of the receiving device is transmitted to the video recorder VCRR with IEEE1394 interface 1394V through the IEEE1394 bus for video recording. At the same time, a DVD pla...

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PUM

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Abstract

The IEEE1394 bus communication protocol has three layers: physical layer, link layer, and transaction layer. A link layer IC implements the interface to an external application and prepares data for sending on the bus, or interprets incoming data packets from the IEEE1394 bus. A physical layer IC implements the direct electrical connection to the bus and controls many functions including arbitration for sending data on the bus. According to the invention the capacity of the on-chip memory becomes assigned in a flexible way in order to be able to meet the requirements for any specific service. Further, the on-chip memory is prevented from storing data packets containing transmission errors by CRC checking on the fly header data and other data. This is performed for asynchronous data packets as well as isochronous data packets, and allows to have a minimum on-chip memory capacity only. <IMAGE>

Description

technical field [0001] The present invention relates to a bus interface and method of a memory used in an integrated circuit, which connects the bus and the application equipment controlled by the bus. Background technique [0002] IEEE1394 bus is a low-cost, high-performance serial bus. This bus has a read / write memory structure and a highly complex communication protocol. It can transmit data close to real-time at a rate of 100, 200, and 400Mbit / s, and can realize two-way transmission of data. The first ten bits of the transport address value are used to correspond to one of 1023 possible IEEE 1324 bus clusters. The next six bits of the transport address value correspond to one of 63 nodes in a particular cluster that is assigned to an application. Data exchange between the joints does not require the interaction of the host controller. Devices can be disconnected or connected to the network at any time, allowing plug and play. [0003] The standard cable length to co...

Claims

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Application Information

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IPC IPC(8): H04L1/00H04L29/06G06F11/10H04L12/40H04L12/64H04L49/901H04N7/173H04N21/436H04N21/4425
CPCH04L1/0061H04L1/0072H04L12/40058H04L12/40071H04L49/90H04L49/901H04L49/9036H04L49/9057H04L49/9084H04L49/9089
Inventor 西格弗里德·施魏德尔托马斯·布鲁内
Owner DEUTSCHE THOMSON-BRANDT GMBH
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