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Multiplier, method, integrated circuit chip and computing device for floating point operation

A multiplier, floating-point number technology, applied in computing, instrumentation, electrical and digital data processing, etc., to achieve the effect of flexible application and reduced layout area

Pending Publication Date: 2021-04-30
ANHUI CAMBRICON INFORMATION TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Although the current multiplier has achieved significant improvements in execution efficiency, there is still room for improvement in handling floating-point data

Method used

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  • Multiplier, method, integrated circuit chip and computing device for floating point operation
  • Multiplier, method, integrated circuit chip and computing device for floating point operation
  • Multiplier, method, integrated circuit chip and computing device for floating point operation

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Embodiment Construction

[0019] The technical solution disclosed in the present disclosure generally provides a multiplier, method, integrated circuit chip and computing device for floating-point calculation. Different from the floating-point multiplier in the prior art, the present disclosure provides a multiplier that supports multiple operation modes, thereby overcoming the defect that the existing multiplier can only support one type of floating-point operation. In particular, the present disclosure utilizes multiple operation modes to indicate different floating-point data types, and in the process of multiplying floating-point numbers, various operations on data are performed based on one of the operation modes, including, for example, encoding, compression, and summation , normalization, and rounding operations to implement operations associated with one of several floating-point data types. Therefore, the multiplier of the present disclosure can support operations in multiple modes, further im...

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Abstract

The present invention relates to a multiplier, a method, an integrated circuit chip and a computing device for a floating point operation, wherein the computing device may be included in a combined processing device, which may also include a universal interconnect interface and other processing devices. The computing device interacts with other processing devices to jointly complete the computing operation specified by the user. The combined processing device can further comprise a storage device, and the storage device is connected with the computing device and the other processing devices and used for storing data of the computing device and the other processing devices. The scheme of the invention can be widely applied to various floating point data operations.

Description

technical field [0001] This disclosure relates generally to the field of floating point arithmetic. More specifically, the present disclosure relates to methods, multipliers, integrated circuit chips and computing devices for floating point operations. Background technique [0002] In various current signal processing algorithms, such as the inner product operation between vectors and the convolution operation of matrices, a large number of multiplication and addition operations are used, and the efficiency of these multiplication and addition operations often depends on the execution speed of the multiplier. Although the current multiplier has been significantly improved in terms of execution efficiency, there is still room for improvement in terms of processing floating-point type data. Therefore, how to obtain a multiplier with high efficiency, low power consumption and low cost to perform the multiplication operation of floating-point data has become a problem to be sol...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F7/523G06F7/57
CPCG06F7/523G06F7/57
Inventor 不公告发明人
Owner ANHUI CAMBRICON INFORMATION TECH CO LTD