Method for evaluating reliability of combined circuit for controlling signal probability of system

Abstract

The invention discloses a method for evaluating the reliability of a combined circuit for controlling the signal probability of a system. The method comprises the following steps: applying an input vector to a circuit, and performing simulating to obtain a normal output signal logic value of each node in the circuit; determining the correct output probability of each logic gate in the circuit, and calculating the value probability that the output of each node is a normal output signal logic value based on the normal output probability; and calculating the reliability of the circuit under the excitation of the input vector based on each value probability, and calculating the total reliability of the circuit under each input vector. According to the method, the normal logic value probabilities of all node signals of the combinational circuit from original input to original output under the excitation of a given input vector are calculated, and the reliability of the circuit affected by soft errors is analyzed in combination with fault simulation, and the condition reliability of the combinational circuit under excitation of a certain specific vector or the average reliability under excitation of a plurality of random directions can be simply, quickly and accurately calculated.

Description

technical field [0001] The present application relates to the technical field of reliability evaluation of large and complex systems, and in particular, relates to a method for evaluating the reliability of a combined circuit of a control system signal probability. Background technique [0002] The control system is the commander and manager of large devices. The control system is composed of many integrated circuits. Very Large-Scale Integrated (VLSI) circuit technology is an important part of modern electronic information technology. The development of economy and national defense construction plays a huge role in promoting. However, with the application of deep submicron and nanometer processes, the integration level of chips continues to increase, and integrated structures are becoming more and more sensitive to radiation. Soft errors caused by high-energy particle bombardment will seriously affect the reliability of circuits. [0003] As the CMOS transistor shrinks to ...

AI Technical Summary

Problems solved by technology

However, with the application of deep submicron and nanometer processes, the integration level of chips continues to increase, and integrated structures are becoming more and more sensitive to radiation. Soft errors caused by high-energy particle bombardment will seriously affect the reliability of circuits.

[0003] With the reduction of CMOS transistors to nanoscale size, the integration level of the circuit will increase sharply, and the probability of causing soft errors will also increase, which will lead to an increase in the failure rate of circuits built with nanoscale transistors.

However, circuit designers cannot accurately evaluate and compare the reliability of different circuits during the circuit design stage.

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