Fieldbus Chip Architecture

Abstract

The invention discloses a field bus chip architecture, which includes a CPU interaction module, a clock management module, a frame encoding / decoding module, a Manchester encoding / decoding module, a RAM data storage module, a DMA controller, a data transceiver module, and a CRC frame check module, address recognition and management module, interrupt controller and register stack. The present invention proposes to package the AXI4 bus protocol interface in the chip, and perform data interaction with the CPU through the AXI4 bus. The handshake mechanism of the AXI4 bus can ensure that the data transmission between the CPU and the chip of the present invention is safe and reliable. The AXI bus ID of the AXI bus, through the ID access chip, realizes that a microprocessor mounts multiple chips of the present invention, and configures the feature code register through the AXI4-Lite bus to realize the field bus protocol data frame encoding and decoding capabilities of the chip.

Description

technical field [0001] The invention belongs to the field of field bus controllers, and in particular relates to a field bus chip architecture. Background technique [0002] The rapid development of computer network technology promotes the continuous change of the architecture of industrial automation control system. The traditional 4-20mA analog signal system is replaced by the two-way digital communication field bus signal system, and the analog and digital distributed control system is replaced by the all-digital field control FCS system. [0003] According to the definition of the International Electrotechnical Commission IEC 1158, the data bus of digital, serial and multipoint communication between the field devices installed in the manufacturing or process area and the automatic control devices in the control room is called field bus. Fieldbus Fieldbus is an industrial data bus developed rapidly in recent years. It mainly solves the digital communication among field d...

AI Technical Summary

Problems solved by technology

[0013] Aiming at the problems that existing chips of this type do not adopt the standard communication bus communication protocol at the CPU interface level, there is no confirmation mechanism for data transmission, and the microprocessor cannot mount multiple field bus chips, the present invention proposes to package the AXI4 bus protocol in the chip Interface, through the AXI4 bus and the CPU for data interaction, the handshake mechanism of the AXI4 bus, that is, the sender and the receiver send confirmation signals to each other, which can ensure that the data transmission between the CPU and the chip of the present invention is safe and reliable; and after using the AXI4 bus, the chip can be Allocate different AXI bus IDs, access chips through IDs, and realize that one microprocessor mounts multiple chips of the present invention

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