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Soft start circuit and FPGA system

A soft-start circuit and capacitor technology, applied in the field of FPGA, can solve the problems of high power load transient and unstable power loop.

Pending Publication Date: 2021-05-18
INSPUR BEIJING ELECTRONICS INFORMATION IND
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

And the large amount of current required to power up the FPGA can cause high load transients on the power supply, leading to instability in the power loop

Method used

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  • Soft start circuit and FPGA system

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Embodiment Construction

[0020] The core of this application is to provide a soft start circuit and FPGA system, which can reduce the influence of excessive load current of the rear stage and pull down the front-end voltage, and ensure the stability of the power supply loop.

[0021] In order to make the purposes, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments It is a part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the scope of protection of this application.

[0022] Please refer to figure 1 , figure 1 A schematic structural diagram of a soft start circuit ...

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Abstract

The invention discloses a soft start circuit which comprises a monitoring module, a driving module and a first switch arranged on a power supply path of a power supply module and an FPGA, wherein the monitoring module is used for monitoring the voltage of the output end of the power supply module and outputting a corresponding control signal according to the voltage; and the driving module is used for adjusting the conduction degree of the first switch according to the control signal so as to adjust the current on the power supply path. According to the invention, the influence caused by that the post-stage load current is overlarge, so that the front-end voltage is lowered, can be reduced, and the stability of a power supply loop is ensured. The invention further discloses an FPGA system which has the above beneficial effects.

Description

technical field [0001] This application relates to the FPGA field, in particular to a soft start circuit and an FPGA system. Background technique [0002] At present, the core power supply current requirements for chips such as FPGA (Field Programmable Gate Array, Field Programmable Logic Gate Array) are getting higher and higher, ranging from tens of amperes to hundreds of amperes, and the specific size is related to the clock frequency and the size of the resources used. The large amount of current required to power up the FPGA can cause high load transients on the power supply, leading to instability in the power loop. [0003] Therefore, how to provide a solution to the above technical problems is a problem that those skilled in the art need to solve at present. Contents of the invention [0004] The purpose of this application is to provide a soft-start circuit and FPGA system, which can reduce the impact of excessive load current in the rear stage and pull down the ...

Claims

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Application Information

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IPC IPC(8): H02H9/02
CPCH02H9/02H02H9/025
Inventor 计晶刘铁军
Owner INSPUR BEIJING ELECTRONICS INFORMATION IND
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