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SRAM storage unit, SRAM and data storage method

A storage unit and storage node technology, which is applied in the semiconductor field and can solve problems such as SRAM information residue

Active Publication Date: 2021-06-01
INST OF MICROELECTRONICS CHINESE ACAD OF SCI
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, SRAM has the problem of information residue, and the information stored before power failure can be partially restored by aging imprint extraction method

Method used

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  • SRAM storage unit, SRAM and data storage method
  • SRAM storage unit, SRAM and data storage method
  • SRAM storage unit, SRAM and data storage method

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Embodiment Construction

[0018] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention.

[0019] Various schematic views of embodiments of the invention are shown in the drawings, which are not drawn to scale. Therein, certain details have been exaggerated and certain details may have been omitted for the sake of clarity. The shapes of the various regions and layers shown in the figure, as well as their relative sizes and positional relationships are only exemplary, and may deviate due to manufacturing tolerances or technical limitations in practice, and those skilled in the art will Regions / layers with different shapes, sizes, and relative positions can be additionally designed as needed.

[0020] Hereinafter, the terms "first", "second", etc. are used ...

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Abstract

The invention discloses an SRAM storage unit, an SRAM memory and a data storage method, and belongs to the field of semiconductors. And the storage data in the SRAM storage unit are continuously exchanged among the storage nodes, so the threshold mismatch is eliminated. A master circuit and a slave circuit are included. The main circuit comprises a first phase inverter and a second phase inverter which are cross-coupled, and a first storage node and a second storage node are formed after the first phase inverter and the second phase inverter are cross-coupled with each other; the slave circuit comprises a first switching circuit which is connected in series between the output end of the second phase inverter and the input end of the first phase inverter; the slave circuit further comprises a second switching circuit, an inverter circuit and a third switching circuit which are sequentially connected in series between the first storage node and the second storage node; and in one storage period, after the first switching circuit, the second switching circuit and the third switching circuit are sequentially controlled according to the first control mode and the second control mode, the storage potential in the first storage node and the storage potential in the second storage node are overturned.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to an SRAM storage unit, an SRAM memory and a data storage method. Background technique [0002] SRAM (Random-Access Memory, static random access memory) is a kind of memory with static access function, which can save the data stored in it without refreshing the circuit. When SRAM is used in a chip, when the chip system detects unauthorized access, the chip system can cut off the power supply of the SRAM to prevent attackers from stealing data. However, SRAM has the problem of information residue, and the information stored before power failure can be partially restored by aging imprint extraction. Among them, aging imprint extraction means that when a memory cell stores fixed data for a long time, two symmetrical transistors will experience different degrees of BTI (Bias Temperature Instability, bias temperature instability) aging effect, resulting in a permanent threshold ...

Claims

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Application Information

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IPC IPC(8): G11C11/417G11C11/419
CPCG11C11/417G11C11/419
Inventor 李博苏泽鑫宿晓慧刘凡宇黄杨罗家俊韩郑生
Owner INST OF MICROELECTRONICS CHINESE ACAD OF SCI
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